
W39V040A
Publication Release Date: December 19, 2002
- 7 -
Revision A2
Continued
100
FFDF, FFFFh: FFD8, 0000h
101
FFD7, FFFFh: FFD0, 0000h
110
FFCF, FFFFh: FFC8, 0000h
111
FFC7, FFFFh: FFC0, 0000h
Table of Operating Modes
Operating Mode Selection - Programmer Mode
PINS
ADDRESS
AIN
AIN
MODE
#OE
V
IL
V
IH
X
V
IL
X
V
IH
#WE
V
IH
V
IL
X
X
V
IH
X
#RESET
V
IH
V
IH
V
IL
V
IH
V
IH
V
IH
DQ.
Read
Write
Standby
Dout
Din
High Z
High Z/DOUT
High Z/DOUT
High Z
X
X
X
X
Write Inhibit
Output Disable
Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is
not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory
Cycle Definition".
Standard LPC Memory Cycle Definition
FIELD
NO. OF
CLOCKS
DESCRIPTION
Start
1
"0000b" appears on LPC bus to indicate the initial
Cycle Type & Dir
1
"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.
TAR
2
Turned Around Time
Addr.
8
Address Phase for Memory Cycle. LPC supports the 32 bits address protocol.
The addresses transfer most significant nibble first and least significant nibble
last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.)
Sync.
N
Synchronous to add wait state. "0000b" means Ready, "0101b" means Short
Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error,
other values are reserved.
Data
2
Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on
LAD[3:0] last.)