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參數(shù)資料
| 型號： | W39L512 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K 8 COMS FLASH MEMORY |
| 中文描述： | 64K的8 COMS衛(wèi)星閃存 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 304K |
| 代理商： | W39L512 |
W39L512
- 6 -
Upon executing the algorithm, the system is not required to provide further controls or timings. The
device will automatically provide adequate internally generated program pulses and verify the
programmed cell margin.
The automatic programming operation is completed when the data on DQ7 (also used as Data Polling)
is equivalent to the data written to this bit at which time the device returns to the read mode and
addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that
a valid address to the device be supplied by the system at this particular instance of time for Data
Polling operations. Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a
hardware reset occurs during the programming operation, the data at that particular location will be
corrupted.
Programming is allowed in any sequence and across page boundaries. Beware that a data "0" cannot
be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only
erase operations can convert "0"s to "1"s.
Refer to the Programming Command Flow Chart using typical command strings and bus operations.
Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the
"set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the
Embedded Erase Algorithm command sequence the device will automatically erase and verify the
entire memory for an all one data pattern. The erase is performed sequentially on each pages at the
same time (see "Feature"). The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and
terminates when the data on DQ7 is "1" at which time the device returns to read the mode.
Refer to the Erase Command Flow Chart using typical command strings and bus operations.
Page Erase Command
Page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by writing the
"set-up" command. Two more "unlock" write cycles then follows by the page erase command. The
page address (any address location within the desired page) is latched on the falling edge of #WE,
while the command (50H) is latched on the rising edge of #WE.
Page erase does not require the user to program the device prior to erase. When erasing a page, the
remaining unselected pages are not affected. The system is not required to provide any controls or
timings during these operations.
The automatic page erase begins after the erase command is completed, right from the rising edge of
the #WE pulse for the last page erase command pulse and terminates when the data on DQ7, Data
Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an
address within any of the pages being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.
相關PDF資料 |
PDF描述 |
|---|---|
| W39L512-70 | 64K 8 COMS FLASH MEMORY |
| W39L512-90 | 64K 8 COMS FLASH MEMORY |
| W39V040AP | 512K 】 8 CMOS FLASH MEMORY WITH LPC INTERFACE |
| W39V040AQ | 512K 】 8 CMOS FLASH MEMORY WITH LPC INTERFACE |
| W39V040BQ | W39V040B |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W39L512-70 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K 8 COMS FLASH MEMORY |
| W39L512-90 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K 8 COMS FLASH MEMORY |
| W39L512P-90 | 制造商:Winbond Electronics Corp 功能描述: |
| W39V040A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K 】 8 CMOS FLASH MEMORY WITH LPC INTERFACE |
| W39V040AP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K 】 8 CMOS FLASH MEMORY WITH LPC INTERFACE |
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