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參數(shù)資料
| 型號： | W28V400T |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY |
| 中文描述： | 4分（為512k × 8/256K × 16）SMARTVOLTA通用閃存 |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 1822K |
| 代理商： | W28V400T |
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W28V400B/T
- 10 -
8. BUS OPERATION
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Read
Information can be read from any block, identifier codes or status register independent of the V
PP
voltage. #RESET can be at either V
IH
or V
HH
.
The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or
Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down
mode, the device automatically resets to read array mode. Six control pins dictate the data flow in and
out of the component: #CE, #OE, #WE, #RESET, #WP and #BYTE. #CE and #OE must be driven
active to obtain data at the outputs. #CE is the device selection control, and when active enables the
selected memory device. #OE is the data output (DQ0
DQ15) control and when active drives the
selected memory data onto the I/O bus. #WE must be at V
IH
and #RESET must be at V
IH
or V
HH
.
Figure 13, 14 illustrates read cycle.
Output Disable
With #OE at a logic-high level (V
IH
), the device outputs are disabled. Output pins (DQ0
DQ15) are
placed in a high-impedance state.
Standby
Setting #CE to a logic-high level (V
IH
) deselects the device and places it in standby mode, which
substantially reduces device power consumption. DQ0
DQ15 outputs are placed in a high
impedance state independent of #OE. If deselected during block erase or word/byte write, the device
continues functioning, and it continues to consume active power until the operation is completed.
Deep Power-down
Setting #RESET to V
IL
initiates the deep power-down mode.
In read modes, setting #RESET at V
IL
deselects the memory, places output drivers in a high-
impedance state and turns off all internal circuits. #RESET must be held low for a minimum of 100 nS.
A delay (t
PHQV
) is required after return from reset until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The CUI is reset to read array mode status register
is set to 80H.
During block erase or word/byte write modes, #RESET at V
IL
will abort the operation. RY/#BY remains
low until the reset operation is complete. Memory contents at the aborted location are no longer valid
since the data may be partially erased or written. A delay (t
PHWL
) is required after #RESET goes to
logic-high (V
IH
) before another command can be written.
As with any automated device, it is important to assert #RESET during system reset. When the
system comes out of reset, it expects to read from the flash memory. Automated flash memories
provide status information when accessed during block erase or word/byte write modes. If a CPU
reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash
memory may be providing status information instead of array data.
Winbond’s flash memories allow proper CPU initialization following a system reset through the use of
the #RESET input. In this application, #RESET is controlled by the same #RESET signal that resets
the system CPU.
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相關(guān)代理商/技術(shù)參數(shù) |
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