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參數(shù)資料
| 型號： | W28F641TT80L |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 64MBIT (4MBIT 】 16) PAGE MODE DUAL WORK FLASH MEMORY |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 9/31頁 |
| 文件大小： | 389K |
| 代理商： | W28F641TT80L |
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W28F641B/T
Publication Release Date: March 27, 2003
- 9 -
Revision A3
Customer programmable Area Lock Bit (DQ1)
Reserved for Future Implementation
(DQ15-DQ2)
Factory Programmed Area
[A21-A0]
000088H
000085H
000084H
000081H
000080H
Customer Programmable Area
Factory programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map for OTP Program (The area outside 80H~88H cannot be used.)
Table 5. Bus Operations
(1, 2)
MODE
NOTE
#RESET
#CE
#OE
#WE
ADDRESS
V
PP
DQ0
15
Read Array
6
V
IH
V
IL
V
IL
V
IH
X
X
DOUT
Output Disable
V
IH
V
IL
V
IH
V
IH
X
X
High Z
Standby
V
IH
V
IH
X
X
X
X
High Z
Reset
3
V
IL
X
X
X
X
X
High Z
Read Identifier
Codes/OTP
6
V
IH
V
IL
V
IL
V
IH
See
Table 3, 4
X
See
Table 3, 4
Read Query
6,7
V
IH
V
IL
V
IL
V
IH
See
Appendix
X
See
Appendix
Write
4,5,6
V
IH
V
IL
V
IH
V
IL
X
X
DIN
Notes:
1. Refer to DC Characteristics. When V
PP
≤
V
PPLK
, memory contents can be read, but cannot be altered.
2. X can be V
IL
or V
IH
for control pins and addresses, and V
PPLK
or V
PPH1/2
for V
PP
. See DC Characteristics for V
PPLK
and V
PPH1/2
voltages.
3. #RESET at V
SS
±
0.2V ensures the lowest power consumption.
4. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when V
PP
= V
PPH1/2
and
V
DD
= 2.7V to 3.6V.
Command writes involving full chip erase are reliably executed when V
PP
= V
PPH1
and V
DD
= 2.7V to 3.6V.
5. Refer to Table 6 for valid DIN during a write operation.
6. Never hold #OE low and #WE low at the same timing.
7. Refer to Appendix for more information about query code.
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