
W28F641B/T
1. GENERAL DESCRIPTION
The W28F641, a 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash
memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide
range of applications. The product can be operated at V
DD
= 2.7V to 3.6V and V
PP
= 1.65V to 3.6V or
11.7V to 12.3V. Its low voltage operation capability greatly extends battery life for portable
applications.
The W28F641 provides high performance asynchronous page mode. It allows code execution directly
from Flash, thus eliminating time-consuming wait states. Furthermore, the configurative partitioning
architecture allows flexible dual work operation.
The memory array block architecture utilizes Enhanced Data Protection features, and provides
separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and
data storage.
Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP
(One Time Program) block provides an area to store permanent code such as a unique number.
2. FEATURES
One hundred and twenty-seven 32k-word
Main Blocks
Top or Bottom Parameter Location
64M Density with 16Bit I/O Interface
High-Performance Reads
80/35 nS 8-Word Page Mode
Configurative 4-Plane Dual Work
Flexible Partitioning
Read operations during Block Erase or (Page
Buffer) Program
Status Register for Each Partition
Low Power Operation
2.7V Read and Write Operations
V
DDQ
for Input/Output Power Supply Isolation
Automatic Power Savings Mode Reduces
I
CCR
in Static Mode
Enhanced Code + Data Storage
5
μ
S Typical Erase/Program Suspends
OTP (One Time Program) Block
4-Word Factory-Programmed Area
4-Word User-Programmable Area
High Performance Program with Page Buffer
16-Word Page Buffer
5
μ
S/ Word (Typ.) at 12V V
PP
Operating Temperature
-40
°
C to +85
°
C
CMOS Process (P-type silicon substrate)
Enhanced Data Protection Features
Individual Block Lock and Block Lock-Down
with Zero-Latency
All blocks are locked at power-up or device
reset
Absolute Protection with V
PP
≤
V
PPLK
Block Erase, Full Chip Erase, (Page Buffer)
Word Program Lockout during Power
Transitions
Automated Erase/Program Algorithms
3.0V Low-Power 11
μ
S/ Word (Typ.)
Programming
12V No Glue Logic 9
μ
S/ Word (Typ.)
Production Programming and 0.5s Erase
(Typ.)
Cross-Compatible Command Support
Common Flash Interface (CFI)
Basic Command Set
Extended Cycling Capability
Minimum 100,000 Block Erase Cycles
Chip-Size Packaging
0.75 mm pitch 48-Ball TFBGA and 48-Pin
TSOP
Flexible Blocking Architecture
Eight 4k-word Parameter Blocks
ETOX Flash Technology
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