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參數資料
| 型號： | AD783 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Complete Very High Speed Sample-and-Hold Amplifier(高速采樣保持放大器) |
| 中文描述： | 完整的超高速采樣保持放大器（高速采樣保持放大器） |
| 文件頁數： | 8/8頁 |
| 文件大小： | 138K |
| 代理商： | AD783 |
AD783
REV. A
–8–
C
P
AD783 T O AD670 INT E RFACE
T he 15 MHz small signal bandwidth of the AD783 makes it a
good choice for undersampling applications. Figure 8 shows
the interface between the AD783 and the AD670 ADC, where
the AD783 samples the incoming IF signal. For this particular
application, the IF carrier was 10.7 MHz and the information
signal was a 5 kHz FSK -modulated tone. T he sample-and-hold
signal is applied to the 8-bit AD670 ADC and then digitally
processed for analysis.
T he CLK IN signal is connected directly to the S/H pin of the
AD783 and must comply with the acquisition and settling re-
quirements of the SHA. A delayed version of CLK IN is applied
to the R/
W
input of the AD670 in order to accommodate the
hold-mode settling requirements of the AD783. T he 10
μ
s con-
version speed of the AD670 combined with the 150 ns hold-
mode settling time of the AD783 result in a total system
throughput of 10.15
μ
s.
By keeping the 10.7 MHz IF input to the AD783 at a low
amplitude, 255 mV p-p, the resultant distortion and jitter-
induced noise result in approximately 45 dB of dynamic range.
T he AD670 can be conveniently configured such that its full-
scale input range is 255 mV in order to retain the full 8-bit
dynamic range of the converter. T he maximum sample rate of
the AD670 is 10
μ
s; therefore, to comply with the Nyquist
criteria the maximum information bandwidth is 50 kHz.
10k
2
7
8
AD670
+V
IN
HI
50
ANALOG
INPUT
CLK IN
10.7MHz
255mV p-p
+V
IN
LOW
–V
IN
HI
–V
IN
LOW
ONE -
SHOT
R/W
AD783
16
17
19
18
21
Figure 8. AD783 to AD670 Interface
AD783 to AD671 (12-Bit, 500 ns ADC) Interface
T he AD783 to AD671 interface requires an op amp, a dual
flip-flop, and a monostable multivibrator or “one-shot.” T he
op amp amplifies the
±
2.5 V output of the AD783 to the
full-scale input of the AD671. Appropriate op amps include the
AD841 and AD845 (see the AD671 data sheet for additional
information). T he flip-flops and one-shot are used to generate
the AD671 ENCODE pulse and the appropriately timed
AD783 S/H pulse.
A master sampling clock is tied to the clock input of flip-flop1
and the input of the one-shot. T he D1 input of flip-flop1
should be tied high and the one-shot should be configured to
generate a pulse on a rising edge of the sampling clock. T he ris-
ing edge of the sampling clock causes the
Q1
output of the
flip-flop to go low placing the AD783 into hold mode. Simulta-
neously, a low going pulse is generated at the one-shot output.
T he length of this pulse would usually be made long enough to
allow the output of the AD783 to settle (hold-mode settling
time), but because of the error-correcting ability of the AD671,
the length of this pulse may be reduced to approximately 200 ns.
T he low going one-shot output is connected to the clock input
of flip-flop2. T he D2 input of flip-flop2 is tied high. T he rising
edge of the low going pulse toggles the Q2 output of flip-flop2 to
a high state. T his output, which is tied to the ENCODE input of
the AD671, initiates a conversion of the buffered output signal
of the AD783. T he AD671 issues the signal DAV when the con-
version is complete. T he DAV signal is tied to the asynchronous
CLR1
and
CLR2
inputs of both flip-flops. When DAV goes low,
the
Q1
output goes high returning the AD783 to the sample or
acquisition mode. T he Q2 output (ENCODE) returns low until
it is again triggered by the rising edge of the one-shot output.
V
IN
AD783
Q2
D1
D2
+5V
CLOCK
DAV
ENCODE
AIN
AD671
AD84X
ONE-
SHOT
Q1
CLR2
CLR1
Figure 9. AD783 to AD671 Interface
OUT LINE DIME NSIONS
Dimensions shown in inches and (mm).
8-Pin Cerdip (Q-8) Package
0.200
(5.08)
MAX
0.100 (2.54)
BSC
0.150
(3.81)
MIN
0.405 (10.29)
MAX
8
1
5
4
0.220 (5.59)
0.310 (7.87)
0.014 (0.36)
0.023 (0.58)
0.015 (0.38)
0.060 (1.52)
0.030 (0.76)
0.070 (1.78)
0.290 (7.37)
0.320 (8.13)
0.008 (0.204)
0.015 (0.381)
8-Pin SOIC (R-8) Package
1
4
5
8
0.050 (1.27)
BSC
0.188 (4.77)
0.198 (5.03)
0.150 (3.81)
0.158 (4.01)
0.224 (5.69)
0.248 (6.29)
0.014 (0.36)
0.022 (0.56)
0.195 (4.95)
0.205 (5.21)
0.089 (2.26)
0.107 (2.72)
0.018 (0.46)
0.034 (0.86)
0.007 (0.18)
0.015 (0.38)
0.005 (0.125)
0.011 (0.275)
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