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參數資料
| 型號： | AD783 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Complete Very High Speed Sample-and-Hold Amplifier(高速采樣保持放大器) |
| 中文描述： | 完整的超高速采樣保持放大器（高速采樣保持放大器） |
| 文件頁數： | 6/8頁 |
| 文件大小： | 138K |
| 代理商： | AD783 |
AD783
REV. A
–6–
DY NAMIC PE RFORMANCE
T he AD783 is compatible with 12-bit A-to-D converters in
terms of both accuracy and speed. T he fast acquisition time, fast
hold settling time and good output drive capability allow the
AD783 to be used with high speed, high resolution A-to-D
converters like the AD671 and AD7586. T he AD783’s fast
acquisition time provides high throughput rates for multichannel
data acquisition systems. T ypically, the AD783 can acquire a
5 V step in less than 250 ns. Figure 1 shows the settling
accuracy as a function of acquisition time.
0.08
0.06
0.04
0.02
0
0
250
500
ACQUISITION TIME – ns
V
O
Figure 1. V
OUT
Settling vs. Acquisition Time
T he hold settling determines the required time, after the hold
command is given, for the output to settle to its final specified
accuracy. T he typical settling behavior of the AD783 is 150 ns.
T he settling time of the AD783 is sufficiently fast to allow the
SHA, in most cases, to directly drive an A-to-D converter
without the need for an added “start convert” delay.
HOLD MODE OFFSE T
T he dc accuracy of the AD783 is determined primarily by the
hold mode offset. T he hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. T he hold mode offset arises
from a voltage error introduced onto the hold capacitor by
charge injection of the internal switches. T he nominal hold
mode offset is specified for a 0 V input condition. Over the in-
put range of –2.5 V to +2.5 V, the AD783 is also characterized
for an effective gain error and nonlinearity of the held value, as
shown in Figure 2. As indicated by the AD783 specifications,
the hold mode offset is very stable over temperature.
NONLINEARITY
GAIN ERROR
V , VOLTS
–2.5
+2.5
+1
HOLD MODE OFFSET
–1
(V
OUT
HOLD – V
IN
), mV
Figure 2. Hold Mode Offset, Gain Error and Nonlinearity
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accom-
plished through the A-to-D itself or by an external amplifier
with offset nulling capability (e.g., AD711). T he offset will
change less than 0.5 mV over the specified temperature range.
SUPPLY DE COUPLING AND GROUNDING
C ONSIDE RAT IONS
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from
excessive high frequency noise (ripple). T he supply connection
to the AD783 should also be capable of delivering transient
currents to the device. T o achieve the specified accuracy and
dynamic performance, decoupling capacitors must be placed
directly at both the positive and negative supply pins to com-
mon. Ceramic type 0.1
μ
F capacitors should be connected from
V
CC
and V
EE
to common.
ANALOG
P.S.
DIGITAL
P.S.
+5V
C
–5V
C
+5V
0.1
μ
F
0.1
μ
F
1
μ
F
1
μ
F
1
μ
F
AD783
DIGITAL
DATA
OUTPUT
SIGNAL GROUND
INPUT
ANALOG-TO-DIGITAL
CONVERTER
Figure 3. Basic Grounding and Decoupling Diagram
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