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參數資料
| 型號： | WCMA4016U1X |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256K x 16 Static RAM |
| 中文描述： | 256K × 16靜態RAM |
| 文件頁數： | 4/9頁 |
| 文件大小： | 164K |
| 代理商： | WCMA4016U1X |
WCMA4016U1X
4
Data Retention Waveform
[5]
Switching Characteristics
Over the Operating Range
[6]
70 ns
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[8]
t
HZBE
WRITE CYCLE
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
Notes:
5.
BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
6.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
/I
and 30 pF load capacitance.
7.
At any given temperature and voltage condition, t
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8.
If both byte enables are toggled together this value is 10ns
9.
t
, t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11.
The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[7, 9]
OE HIGH to High Z
[9]
CE
1
LOW and CE
2
HIGH to Low Z
[7]
CE
1
HIGH and CE
2
LOW to High Z
[7, 9]
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH and CE
2
LOW to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
35
5
25
10
25
0
70
70
5
25
Write Cycle Time
CE
1
LOW and CE
2
HIGH
to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
70
60
60
0
0
50
ns
ns
ns
ns
ns
ns
V
CC
, min.
t
R
V
CC
, min.
t
CDR
V
DR
> 1.0 V
DATA RETENTION MODE
CE1 or
BHE.BLE
or
V
CC
CE2
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