
WCFS0808V1E
Document #: 38-05225 Rev. **
Page 4 of 10
Switching Characteristics
Over the Operating Range
[5]
WCFS0808V1E 12ns
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[8, 9]
Read Cycle Time
12
ns
Address to Data Valid
12
ns
Data Hold from Address Change
3
ns
CE LOW to Data Valid
12
ns
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
5
ns
0
ns
5
ns
3
ns
6
ns
CE LOW to Power-Up
0
ns
CE HIGH to Power-Down
12
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
12
ns
CE LOW to Write End
8
ns
Address Set-Up to Write End
8
ns
Address Hold from Write End
0
ns
Address Set-Up to Write Start
0
ns
WE Pulse Width
8
ns
Data Set-Up to Write End
7
ns
Data Hold from Write End
WE LOW to High Z
[8]
WE HIGH to Low Z
[6]
0
ns
7
ns
3
ns
Notes:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified I
/I
and capacitance C
= 30 pF.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
t
, t
, t
are specified with C
= 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
6.
7.
8.
9.