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參數資料
| 型號： | WB1356 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual Serial Input PLL with 2.0- and 1.1-GHz Prescalers(帶2.0-GHz1.1-GHz 預標定器的雙路串聯輸入PLL) |
| 中文描述： | 雙串行輸入鎖相環和1.1與2.0 GHz的分頻器（帶2.0 - GHz1.1 - GHz的預標定器的雙路串聯輸入鎖相環） |
| 文件頁數： | 8/10頁 |
| 文件大小： | 157K |
| 代理商： | WB1356 |
WB1356
8
Notes:
6.
7.
The MSB is loaded in first.
Low count ratios may violate frequency limits of the phase detector.
Table 2. Shift Register Configuration
[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Reference Counter and Configuration Bits
CNT1CNT2 R1
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12 R13 R14 R15
FC
IDO
TS
LD
FO
Programmable Counter bits
CNT1CNT2 A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 PRE PD
Bit(s) Name
Function
CNT1, CNT2
Control Bits:
Directs programming data to PLL1 (high frequency) or PLL2 (low frequency).
Reference Counter Setting Bits:
15 bits, R = 3 to 32767.
[7]
R1
–
R15
FC
Phase Sense of the Phase Detector:
Set to match the VCO polarity, H = + (Positive VCO transfer function).
Charge Pump Setting Bit:
ID
O
HIGH = 4.4 mA, ID
O
LOW = 1.1 mA.
Three-state Bit:
Three-states the D
O
output for PLL2 and PLL1 when HIGH.
Lock Detect:
Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when
locked. When not locked, this pin is LOW.
Frequency Out:
This bit can be set to read out reference or programmable divider at the LD pin for test purposes.
ID
O
TS
LD
F
O
PRE
Prescaler:
Prescaler divide bit, for PLL1 and PLL2 (LOW = 64/65, HIGH = 128/129).
Power-down:
LOW = power-up, HIGH = power-down. F
IN
is at a high-impedance state, respective B counter
is disabled, forces three-state at D
O
outputs and phase comparators are disabled. The reference counter is
disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be input and latched
in the power-down state.
PD
A1
–
A7
Swallow Counter Divide Ratio:
A = 0 to 127.
Programmable Counter Divide Ratio:
B = 3 to 2047.
[7]
B1
–
B11
Table 3. F
O
/LD Pin Truth Table
FO (Bit 22)
PLL1
LD (Bit 21)
F
O
/LD Pin Output State
PLL2
PLL1
PLL2
0
0
0
0
Disable
0
0
0
1
PLL2 Lock Detect
0
0
1
0
PLL1 Lock Detect
0
0
1
1
PLL1/PLL2 Lock Detect
0
1
X
0
PLL2 Reference Divider Output
1
0
X
0
PLL1 Reference Divider Output
0
1
X
1
PLL2 Programmable Divider Output
1
0
X
1
PLL1 Programmable Divider Output
1
1
0
1
PLL2 Counter Reset
1
1
1
0
PLL1 Counter Reset
1
1
1
1
PLL1/PLL2 Counter Reset
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