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參數資料
| 型號： | WB1225 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Serial Input PLL with 2.5-GHz Prescaler(帶2.5-GHz 預標定器的串聯輸入PLL) |
| 中文描述： | 串行輸入鎖相環2.5 - GHz的預分頻器（帶2.5 - GHz的預標定器的串聯輸入鎖相環） |
| 文件頁數： | 7/9頁 |
| 文件大小： | 141K |
| 代理商： | WB1225 |
WB1225
7
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins.
Two control bits direct data into the locations given in
Table 1
.
Notes:
2.
3.
4.
5.
6.
7.
t1
–
t5 = 50 μs > t > 0.5 μs.
CLOCK may remain HIGH after latching in data.
DATA is shifted in with the MSB first.
For DATA definitions, refer to
Table 2
.
The MSB is loaded in first.
Low count ratios may violate frequency limits of the phase detector.
Serial Data Input Timing Waveform
[2, 3, 4, 5]
Timing Waveforms
(continued)
CLOCK
//
t2
LE
//
//
//
//
//
//
//
t1
t3
t4
t5
DATA
B11 = MSB
B10
B1
A7
A1
CNT = LSB
Table 1. Control Configuration
CNT
1
Function
Reference Counter:
R = 3 to 16383, set prescaler ratio PRE =0:64/65, PRE=1:32/33
0
Program Counter:
A = 0 to 63, B = 3 to 2047
Table 2. Shift Register Configuration
[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Reference Counter and Configuration Bits
CNT
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
PRE
Programmable Counter Bits
CNT
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
Bit(s) Name
Function
CNT
Control Bit:
Directs programming data to reference or programmable counters.
Reference Counter Setting Bits:
14 bits, R = 3 to 16383.
[7]
R1
–
R14
PRE
Prescaler Divide Bit:
LOW = 64/65 and HIGH = 32/33.
Swallow Counter Divide Ratio:
A = 0 to 63.
Programmable Counter Divide Ratio:
B = 3 to 2047.
[7]
A1
–
A7
B1
–
B11
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