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參數資料
| 型號： | WB1220 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Serial Input PLL with 2.0-GHz Prescaler(帶2.0 GHz 預標定器的串行輸入PLL) |
| 中文描述： | 串行輸入鎖相環2.0 - GHz的預分頻器（帶2.0 GHz的預標定器的串行輸入鎖相環） |
| 文件頁數： | 3/9頁 |
| 文件大小： | 141K |
| 代理商： | WB1220 |
WB1220
3
Pin Definitions
Pin Name
OSC_IN
Pin
No.
1
Pin
Type
I
Pin Description
Oscillator Input:
This input has a V
CC
/2 threshold and CMOS logic level sensitivity.
No Connect
Oscillator Output
NC
2
OSC_OUT
3
O
V
P
V
CC
4
P
Charge Pump Rail Voltage:
This supply for charge pump. Must be > V
CC
.
Power Supply Connection for PLL:
When power is removed from V
CC
all latched
data is lost.
Charge Pump Output:
The phase detector gain is I
P
/2
π
. Sense polarity can be re-
versed by setting FC LOW (pin 15).
Analog and Digital Ground Connection:
This pin must be grounded.
5
P
D
O
6
O
GND
7
G
LD
8
O
Lock Detect Pin:
This output is HIGH with narrow LOW pulses when the loop is locked.
No Connect
NC
9
F
IN
CLOCK
10
I
Input to Prescaler:
Maximum frequency 2.0 GHz.
Data Clock Input:
One bit of data is loaded into the Shift Register on the rising edge
of this signal.
11
I
NC
12
No Connect
Serial Data Input
DATA
13
I
LE
14
I
Load Enable:
On the rising edge of this signal, the data stored in the Shift Register is
latched into the counters and configuration controls.
F
C
15
I
Phase Sense Control for Phase Detector with Internal Pull-up:
When pulled LOW,
the polarity of the Phase Detector is reversed.
BISW
16
O
Analog Switch Output:
Connects to output of charge pump when LE is HIGH.
Monitor Point for Phase Detector Input
F
OUT
P
PWDN
17
O
18
O
External Charge Pump Output:
Open drain N-Channel FET, pull-up resistor required.
19
I
Power Down Pin with Internal Pull-up:
When pin is HIGH, device is in normal state.
When pin is LOW, device is in power-down mode. When device enters power-down
mode the charge pump is in the three-state condition.
External Change Pump:
(CMOS logic output).
R
20
O
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