- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363900 > W79E227AFG (WINBOND ELECTRONICS CORP) 8-BIT MICROCONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | W79E227AFG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-48 |
| 文件頁(yè)數(shù)： | 91/200頁(yè) |
| 文件大小： | 3644K |
| 代理商： | W79E227AFG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)當(dāng)前第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)
Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 91 -
Revision A2.0
11. INTERRUPTS
The device has a four priority level interrupt structure with 20 interrupt sources. Each of the interrupt
sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, all the interrupts
can be globally enabled or disabled.
11.1 Interrupt Sources
The External Interrupts
INT0
and
INT1
can be either edge triggered or level triggered, depending on
bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the
external interrupts are sampled every machine cycle, they have to be held high or low for at least one
complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the
level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is
serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the
interrupt continues to be held low even after the service routine is completed, then the processor may
acknowledge another interrupt request from the same source. Note that the external interrupts INT2
are edge trigger only. By default, the individual interrupt flag corresponding to external interrupt 2 to 5
must be cleared manually by software. It can be configured with hardware cleared by setting the
corresponding bit HCx in T2MOD register. For instance, if HC2 is set hardware will clear IE2 flag after
program enters the interrupt 2 service routine. While for INT3 to INT5 can detect the rising, falling or
both edges which function are selectable by software located in INTCTRL [5:0] register. The Timer 0
and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the overflow in the
Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when the
timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of the TF2 and the EXF2
flags. These flags are set by overflow or capture/reload events in the timer 2 operation. The hardware
does not clear these flags when a timer 2 interrupt is executed. Software has to resolve the cause of
the interrupt between TF2 and EXF2 and clear the appropriate flag.
When ADC conversion is completed hardware will set flag ADCI to logic high to request ADC interrupt
if bit EADC (IE.6) is in high state. ADCI is cleared by software only.
The I2C function can generate interrupt, if EI2C and EA bits are enabled, when SI Flag is set due to a
new I2C status code is generated, SI flag is generated by hardware and must be cleared by software.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-
out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is
enabled by the enable bit EIE.4, then an interrupt will occur.
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to
disable all interrupts.
11.2 Priority Level Structure
There are four priority levels for the interrupts; highest, high, low and lowest. The other interrupt
source can be individually set to either high or low levels. Naturally, a higher priority interrupt cannot
be interrupted by a lower priority interrupt. However there exists a predefined hierarchy amongst the
interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve
simultaneous requests having the same priority level. This hierarchy is defined as shown below; the
interrupts are numbered starting from the highest priority to the lowest.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W79E227APG | 8-BIT MICROCONTROLLER |
| W79E532 | 8-BIT MICROCONTROLLER |
| W79E532A40DL | 8-BIT MICROCONTROLLER |
| W79E532A40DN | 8-BIT MICROCONTROLLER |
| W79E532A40FL | 8-BIT MICROCONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W79E227ALG | 制造商:Nuvoton Technology Corp 功能描述:IC MCU 64K EPROM FLASH 48LQFP |
| W79E227APG | 制造商:Nuvoton Technology Corp 功能描述:IC MCU 64K EPROM FLASH 44PLCC |
| W79E342 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:W79E342 datasheet |
| W79E4051_2051 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:W79E4051_2051_SC7（中文） |
| W79E4051_W79E2051 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:W79E4051_W79E2051 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。