
Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 15 -
Revision A2.0
Due to overlapping of AUX-RAM, NVM data memory and external data memory physical address, the
following table is defined. EnNVM bit (NVMCON.5) will enable read access to NVM data memory
area. DME0 (PMR.0) will enable read access to AUX-RAM.
ENNVM
DME0
DATA MEMORY AREA
0
0
Enable External RAM read/write access by MOVX
0
1
Enable AUX-RAM read/write access by MOVX
1
X
Enable NVM data Memory read access by MOVX only. If EER or
EWR is set and NVM flash erase or write control is busy, to set
this bit read NVM data is invalid.
Table 6-1: Bits setting for MOVX access to Data Memory Area
ENNVM = 1
NVM SIZE = SRAM (1K)
INSTRUCTIONS
ADDR
≤
1K
ADDR > 1K
MOVX A, @DPTR (Read)
NVM
1
Ext memory
1
MOVX A, @R0 (Read)
NVM
2
NOP
Read
access
MOVX A, @R1 (Read)
NVM
2
NOP
MOVX @DPTR, A (Write)
NOP
Ext memory
1
MOVX @R0, A (Write)
NOP
NOP
Write
access
MOVX @R1, A (Write)
NOP
NOP
Table 6-2: W79E225 MOVX read/write access destination
ENNVM = 1
NVM SIZE = SRAM (2K)
INSTRUCTIONS
ADDR
≤
2K
ADDR > 2K
MOVX A, @DPTR (Read)
NVM
1
Ext memory
1
MOVX A, @R0 (Read)
NVM
2
NOP
Read
access
MOVX A, @R1 (Read)
NVM
2
NOP
MOVX @DPTR, A (Write)
NOP
Ext memory
1
MOVX @R0, A (Write)
NOP
NOP
Write
access
MOVX @R1, A (Write)
NOP
NOP
Table 6-3: W79E227 MOVX read/write access destination
Note:
1.
2.
A15~A0=DPTR
A15~A8=XRAMAH