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參數(shù)資料
| 型號(hào)： | W79E217A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁(yè)數(shù)： | 144/207頁(yè) |
| 文件大小： | 3738K |
| 代理商： | W79E217A |
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Preliminary W79E217A Data Sheet
Publication Release Date: December 14, 2007
- 144 -
Revision A3.0
17. I2C SERIAL PORTS
The I2C bus uses two wires (SCL and SDA) to transfer information between devices connected to the
bus. The main features of the I2C bus are:
– Bi-directional data transfer between masters and slaves.
– Multi-master bus (no central master).
– Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.
– Serial clock synchronization allows devices with different bit rates to communicate via one serial
bus.
– Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial
transfer.
– The I2C bus may be used for test and diagnostic purposes.
t
BUF
STOP
SDA
SCL
START
t
HD;STA
t
LOW
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
Repeated
START
t
SU;STA
t
SU;STO
STOP
t
r
Figure 17-1: I2C Bus Timing
The device’s on-chip I2C logic provides the serial interface that meets the I2C bus standard mode
specification. The I2C logic handles bytes transfer autonomously. It also keeps track of serial
transfers, and a status register (I2STATUS) reflects the status of the I2C bus.
The I2C port, SCL and SDA are at P2.6 and P2.7. When the I/O pins are used as I2C port, user must
set the pins to logic high in advance. When I2C port is enabled by setting ENS to high, the internal
states will be controlled by I2CON and I2C logic hardware. Once a new status code is generated and
stored in I2STATUS, the I2C interrupt flag (SI) will be set automatically. If both EA and EI2C are also
in logic high, the I2C interrupt is requested. The 5 most significant bits of I2STATUS stores the internal
state code, the lowest 3 bits are always zero and the content keeps stable until SI is cleared by
software.
17.1 SIO Port
The SIO port is a serial I/O port, which supports all transfer modes from and to the I2C bus. The SIO
port handles byte transfers autonomously. To enable this port, the bit ENS1 in I2CON should be set to
'1'. The CPU interfaces to the SIO port through the seven special function registers. The detail
description of these registers can be found in the I2C Control registers section. The SIO H/W
interfaces to the I2C bus via two pins: SDA (P2.7, serial data line) and SCL (P2.6, serial clock line).
Pull up resistor is needed for Pin P2.6 and P2.7 for I2C operation as these are 2 open drain pins.
17.2 The I2C Control Registers
The I2C has 1 control register (I2CON) to control the transmit/receive flow, 1 data register (I2DAT) to
buffer the Tx/Rx data, 1 status register (I2STATUS) to catch the state of Tx/Rx, recognizable slave
address register for slave mode use and 1 clock rate control block for master mode to generate the
variable baud rate.
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