
W78LE365
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
EA
I
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
the
EA
pin is high.
PSEN
O H
PROGRAM STORE ENABLE:
PS
Port 0 address/data bus. When internal ROM access is performed, no
strobe signal outputs originate from this pin.
enables the external ROM data in the
EN
PS
EN
ALE
O H
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RST
I L
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
XTAL1
I
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2
O
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
V
SS
I
GROUND: ground potential.
V
DD
I
POWER SUPPLY: Supply voltage for operation.
P0.0
P0.7
I/O D PORT 0: Function is the same as that of standard 8052.
P1.0
P1.7
I/O H PORT 1: Function is the same as that of standard 8052.
P2.0
P2.7
I/O H
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory. The P2.6
and P2.7 also provide the alternate function
REBOOT which is H/W reboot
from LD flash.
P3.0
P3.7
I/O H PORT 3: Function is the same as that of the standard 8052.
P4.0
P4.7
I/O H
PORT 4: A bi-directional I/O. The P4.3 also provide the alternate function
REBOOT
which is H/W reboot from LD flash.
* Note:
TYPE
I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Publication Release Date: August 5, 2004
- 5 -
Revision A2