
W78E354
- 24 -
Conversion time: <150
×
12/Fosc sec.
4 channels selected by an analog multiplexer
(ADCS1, ADCS0)
(0, 0)
(0, 1)
(1, 0)
(1, 1)
Selected Channel
ADC0
ADC1
ADC2
ADC3
Set bits ADCS1 and ADCS2 in CONTREG1 to select one of the four analog input channels. The ADC
conversion is started by setting bit ADCSTRT in CONTREG1 using software. When the conversion is
comple, the ADCSTRT bit is cleared by hardware to stop the ADC operation. The ADCINT bit in
INTVECT is set by hardware at the same time.
K. PWM DACs
There are two/fourteen 12/8-bit PWM SDACs and one/three 12/8-bit PWM DDACs in this chip. All
the DAC output buffers have slew rate control to prevent the slew rate from being too large.
Additionally, their outputs are delay-controlled and divided into three groups with different delay times
as follows:
1. Delay about 5ns: BSDAC1, SDAC2, 5, 8, 11, DDAC1.
2. Delay about 10ns: SDAC0, 3, 6, 9, 12, DDAC2.
3. No delay: for the others.
Functional Descriptions:
a. 14 channels of 8-bit Static DAC
The Static DACs are used to generate DC voltages (0
5V). There are 14 registers each
corresponding to one 8-bit PWM 14 channel outputs. Unused PWM channels can be used as a
standard output pin, as these pins can supply 0V or 5V.
The duty cycle of the PWM output = Register value
÷
255
The DC voltage after the low pass filter = V
CC
×
duty cycle
REG. VALUE
DUTY CYCLE
DC VOLTAGE
0
0/255
0V
1
1/255
1/255
×
5V
n/255
×
5V
+5V
n
n/255
255
255/255
The PWM frequency FPWM = Fclock
÷
255
16 MHz
18.432 MHz
20 MHz
24 MHz
F
PWM
62.745 KHz
72.282 KHz
78.431 KHz
94.117 KHz
T
PWM
15.94
μ
S
13.83
μ
S
12.75
μ
S
10.62
μ
S