
Preliminary W77LE58
Publication Release Date: August 1999
- 75 - Revision A1
Movx Characteristics Using Strech Memory Cycles, continued
PARAMETER
SYMBOL
VARIABLE
CLOCK
MIN.
0.5 t
CLCL
- 5
1.5 t
CLCL
- 5
t
CLCL
- 5
2.0 t
CLCL
- 5
VARIABLE
CLOCK
MAX.
0.5 t
CLCL
+ 5
1.5 t
CLCL
+ 5
UNITS
STRECH
ALE Low to
RD
or
WR
Low
t
LLWL
nS
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
Port 0 Address to
RD
or
WR
Low
t
AVWL
nS
Port 2 Address to
RD
or
WR
Low
Data Valid to WR Transition
t
AVWL2
1.5 t
CLCL
- 5
2.5 t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
t
QVWX
-5
1.0 t
CLCL
- 5
t
CLCL
- 5
2.0 t
CLCL
- 5
nS
t
MCS
= 0
t
MCS
>0
t
MCS
= 0
t
MCS
>0
Data Hold after Write
t
WHQX
nS
RD
Low to Address Float
RD
or WR high to ALE high
t
RLAZ
0.5 t
CLCL
- 5
nS
t
WHLH
0
1.0 t
CLCL
- 5
10
1.0 t
CLCL
+ 5
nS
t
MCS
= 0
t
MCS
>0
Note: t
MCS
is a time period related to the Stretch memory cycle selection. The following table shows the time period of t
MCS
for each selection of the Stretch value.
M2
M1
M0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MOVX Cycles
2 machine cycles
3 machine cycles
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
t
MCS
0
4 t
CLCL
8 t
CLCL
12 t
CLCL
16 t
CLCL
20 t
CLCL
24 t
CLCL
28 t
CLCL
EXPLANATION OF LOGIC SYMBOLS
In order to maintain compatibility with the original 8051 family, this device specifies the same
parameter for each device, using the same symbols. The explanation of the symbols is as follows.
t
Time
A
C
Clock
D
H
Logic level high
L
Address
Input Data
Logic level low
I
Instruction
P
PSEN
Q
Output Data
R
RD signal
V
X
Valid
No longer a valid state
W
Z
WR signal
Tri-state