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參數(shù)資料
型號(hào): W77E058A40PL
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝: ROHS COMPLIANT, PLASTIC, LCC-44
文件頁(yè)數(shù): 72/87頁(yè)
文件大小: 594K
代理商: W77E058A40PL
W77E058A
- 72 -
16. ON-CHIP FLASH EPROM CHARACTERISTICS
The W77E058 has several modes to program the on-chip Flash EPROM. All these operations are
configured by the pins RST, ALE,
PSEN
, A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
OECTRL(P3.3),
CE
(P3.6),
OE
(P3.7), A0(P1.0) and V
PP
(
EA
). Moreover, the A15
A0(P2.7
P2.0,
P1.7
P1.0) and the D7
D0(P0.7
P0.0) serve as the address and data bus respectively for these
operations.
Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
Output Disable Condition
When the
OE
is set to high, no data output appears on the D7..D0.
Program Operation
This operation is used to program the data to Flash EPROM and the security bits. Program operation
is done when the V
PP
is reach to V
CP
(12.5V) level,
CE
set to low, and
OE
set to high.
Program Verify Operation
All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.
Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the Flash
EPROM cells and the security bits from 0 to 1. This erase operation is done when the V
PP
is reach to
V
EP
level,
CE
set to low, and
OE
set to high.
Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if V
PP
= V
EP
(14.5V),
CE
is high and
OE
is low.
Program/Erase Inhibit Operation
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6(
CE
) = V
IH
, P3.7(
OE
) = V
IH
, erasing or programming of non-targeted chips is inhibited. So,
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
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