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參數資料
型號: W742S81A
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER
中文描述: 4-BIT, FLASH, 3.58 MHz, MICROCONTROLLER, PQFP100
文件頁數: 23/47頁
文件大?。?/td> 242K
代理商: W742S81A
W742S81A
HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released.
HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released.
HEF.2 = 1 Signal change at port RC causes Hold mode to be released.
HEF.3, HEF.5 & HEF.6 are reserved.
HEF.4 = 1 Overflow from the Divider 1 causes Hold mode to be released.
HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released.
Publication Release Date: March 2003
- 23 -
Revision A1
6.15.2 Interrupt Enable Flag (IEF)
The interrupt enable flag is organized as a 8-bit binary register (IEF.0 to IEF.7). These bits are used to
control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding to the bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disable till the instruction MOV IEF, #I
or EN
INT
is executed again. Otherwise, these interrupts can be disable by executing DIS INT instruction. The bit
descriptions are as follows:
5
6
7
Note: W means write only.
IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0.
IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0.
IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC.
IEF.3, IEF.5 & IEF.6 are reserved.
IEF.4 = 1 Interrupt 4 is accepted by overflow from the Divider 1.
IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.
w
1
2
3
IEF
4
w
w
0
w
w
6.15.3 Port Enable Flag (PEF)
The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be used to
release the hold mode or preform interrupt function, the content of the PEF must be set first. The PEF is
controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:
1
2
3
PEF
Note: W means write only.
PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt.
PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt.
PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt.
PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.
w
w
w
0
w
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