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參數資料
| 型號： | W6810 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | Codec |
| 英文描述： | SINGLE-CHANNEL VOICEBAND CODEC |
| 中文描述： | 單通道聲帶編解碼器 |
| 文件頁數： | 7/36頁 |
| 文件大小： | 405K |
| 代理商： | W6810 |
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W6810
Publication Release Date: October 10, 2002
- 7 -
Revision A9
6. PIN DESCRIPTION
Pin
Name
Pin
No.
Functionality
V
REF
1
This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be decoupled to V
SS
through a 0.1
μ
F ceramic decoupling capacitor. No external loads should be tied to this pin.
RO-
2
Inverting output of the receive smoothing filter. This pin can typically drive a 2 k
load to 1.575
volt peak referenced to the analog ground level.
PAI
3
This pin is the inverting input to the power amplifier. Its DC level is at the V
AG
voltage.
Inverting power amplifier output. This pin can drive a 300
load to 1.575 volt peak referenced
to the V
AG
voltage level.
Non-inverting power amplifier output. This pin can drive a 300
load to 1.575 volt peak
referenced to the V
AG
voltage level.
Power supply. This pin should be decoupled to V
SS
with a 0.1
μ
F ceramic capacitor.
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
PAO-
4
PAO+
5
V
DD
6
FSR
7
PCMR
8
PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR
9
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
selected when this pin is tied to V
SS
. The IDL mode is selected when this pin is tied to V
DD
.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI
10
Power up input signal. When this pin is tied to V
DD
, the part is powered up. When tied to V
SS
,
the part is powered down.
MCLK
11
System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544
kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have
the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the
case of 256 and 512 kHz frequency.
BCLKT
12
PCM transmit bit clock input pin.
PCMT
13
PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
FST
14
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
V
SS
μ
/A-Law
15
This is the supply ground. This pin should be connected to 0V.
16
Compander mode select pin.
μ
-Law companding is selected when this pin is tied to V
DD
. A-Law
companding is selected when this pin is tied to V
SS
.
Analog output of the first gain stage in the transmit path.
AO
17
AI-
18
Inverting input of the first gain stage in the transmit path.
AI+
19
Non-inverting input of the first gain stage in the transmit path.
V
AG
20
Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal
processing. This pin should be decoupled to V
SS
with a 0.01
μ
F capacitor. This pin becomes
high impedance when the chip is powered down.
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PDF描述 |
|---|---|
| W6810IE | SINGLE-CHANNEL VOICEBAND CODEC |
| W6810IR | SINGLE-CHANNEL VOICEBAND CODEC |
| W6810IS | SINGLE-CHANNEL VOICEBAND CODEC |
| W6810IW | SINGLE-CHANNEL VOICEBAND CODEC |
| W6811 | 2-WIRE FIELD PROGRAMMABLE W/TIN PLATING |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W6810_06 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:SINGLE-CHANNEL VOICEBAND CODEC |
| W6810_1 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:Codec Evaluation System User’s Guide |
| W68101W | 制造商:Winbond Electronics Corp 功能描述: |
| W68104J100E | 制造商:Mallory 功能描述:RF410X100V .2 BOX 5% |
| W6810DK | 功能描述:KIT DEV/EVAL FOR W6810 RoHS:否 類別:編程器，開發系統 >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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