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參數資料
| 型號： | W65C02SQ-14 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數： | 3/40頁 |
| 文件大小： | 1011K |
| 代理商： | W65C02SQ-14 |
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The Western Design Center, Inc.
W65C02S Data Sheet
TABLE OF CONTENTS
1
INTRODUCTION................................................................................................................................................................................5
1.1
F
EATURES OF THE
W65C02S
.....................................................................................................................................................5
2
FUNCTIONAL DESCRIPTION......................................................................................................................................................6
2.1
I
NSTRUCTION
R
EGISTER
(IR)
AND
D
ECODE
...........................................................................................................................6
2.2
T
IMING
C
ONTROL
U
NIT
(TCU)
.................................................................................................................................................6
2.3
A
RITHMETIC AND
L
OGIC
U
NIT
(ALU)
.....................................................................................................................................6
2.4
A
CCUMULATOR
R
EGISTER
(A)
...................................................................................................................................................6
2.5
I
NDEX
R
EGISTERS
(X
AND
Y)
......................................................................................................................................................6
2.6
P
ROCESSOR
S
TATUS
R
EGISTER
(P)
...........................................................................................................................................6
2.7
P
ROGRAM
C
OUNTER
R
EGISTER
(PC)
.......................................................................................................................................6
2.8
S
TACK
P
OINTER
R
EGISTER
(S)
..................................................................................................................................................7
3
PIN FUNCTION DESCRIPTION ...................................................................................................................................................9
3.1
A
DDRESS
B
US
(A0-A15)
...............................................................................................................................................................9
3.2
B
US
E
NABLE
(BE)
..........................................................................................................................................................................9
3.3
D
ATA
B
US
(D0-D7)
........................................................................................................................................................................9
3.4
I
NTERRUPT
R
EQUEST
(IRQB)
....................................................................................................................................................9
3.5
M
EMORY
L
OCK
(MLB)
...............................................................................................................................................................9
3.6
N
ON
-M
ASKABLE
I
NTERRUPT
(NMIB)
......................................................................................................................................9
3.7
N
O
C
ONNECT
(NC)
.....................................................................................................................................................................10
3.8
P
HASE
2
I
N
(PHI2),
P
HASE
2
O
UT
(PHI2O)
AND
P
HASE
1
O
UT
(PHI1O)
......................................................................10
3.9
R
EAD
/W
RITE
(RWB)
.................................................................................................................................................................10
3.10
R
EADY
(RDY)
..............................................................................................................................................................................10
3.11
R
ESET
(RESB)
.............................................................................................................................................................................11
3.12
S
ET
O
VERFLOW
(SOB)
..............................................................................................................................................................11
3.13
SYNC
HRONIZE WITH
O
P
C
ODE FETCH
(SYNC)
...................................................................................................................11
3.14
P
OWER
(VDD)
AND
G
ROUND
(VSS)
........................................................................................................................................11
3.15
V
ECTOR
P
ULL
(VPB)
.................................................................................................................................................................11
4
ADDRESSING MODES ...................................................................................................................................................................16
4.1
A
BSOLUTE A
..................................................................................................................................................................................16
4.2
A
BSOLUTE
I
NDEXED
I
NDIRECT
(
A
,
X
)
......................................................................................................................................16
4.3
A
BSOLUTE
I
NDEXED WITH
X
A
,
X
.............................................................................................................................................16
4.4
A
BSOLUTE
I
NDEXED WITH
Y
A
,
Y
............................................................................................................................................17
4.5
A
BSOLUTE
I
NDIRECT
(
A
)
............................................................................................................................................................17
4.6
A
CCUMULATOR
A
.......................................................................................................................................................................17
4.7
I
MMEDIATE
A
DDRESSING
#
.......................................................................................................................................................17
4.8
I
MPLIED I
.......................................................................................................................................................................................17
4.9
P
ROGRAM
C
OUNTER
R
ELATIVE R
...........................................................................................................................................18
4.10
S
TACK S
.........................................................................................................................................................................................18
4.11
Z
ERO
P
AGE ZP
..............................................................................................................................................................................18
4.12
Z
ERO
P
AGE
I
NDEXED
I
NDIRECT
(
ZP
,
X
)
..................................................................................................................................18
4.13
Z
ERO
P
AGE
I
NDEXED WITH
X
ZP
,
X
.........................................................................................................................................19
4.14
Z
ERO
P
AGE
I
NDEXED WITH
Y
ZP
,
Y
........................................................................................................................................19
4.15
Z
ERO
P
AGE
I
NDIRECT
(
ZP
)
........................................................................................................................................................19
4.16
Z
ERO
P
AGE
I
NDIRECT
I
NDEXED WITH
Y
(
ZP
),
Y
..................................................................................................................19
5
OPERATION TABLES ....................................................................................................................................................................21
The Western Design Center, Inc. W65C02S Data Sheet
3
6
DC, AC AND TIMING CHARACTERISTICS .........................................................................................................................23
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相關代理商/技術參數 |
參數描述 |
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| W65C134S8PL-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| W65C134S8PLG-14 | 制造商:Western Design Center (WDC) 功能描述:8-bit Microcontrollers - MCU 8-bit Microcontroller |
| W65C134S8PLG-8 | 功能描述:8位微控制器 -MCU 8-bit Microcontroller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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