
The Western Design Center, Inc.
W65C02S Datasheet
The Western Design Center, Inc. W65C02S Datasheet 33
Address Mode
8b. Stop the Clock i
STP
1 OpCode, 1 byte, 3 cycles
Note
Cycle
1
2
3
1c
1b
1a
1
1
2
3
1
1
2
1
VPB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MLB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SYNC
1
0
0
0
0
0
1
1
0
0
1
1
0
1
Address Bus
PC
PC+1
PC+1
PC+1
PC+1
PC+1
PC+1
PC
PC+1
PC+1
PC+1
PC
PC+1
New PC
Data Bus
OpCode
IO
IO
RES(BRK)
RES(BRK)
RES(BRK)
BEGIN
OpCode
IO
IO
IRQ(BRK)
OpCode
Offset
OpCode
RWB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESB=1
RESB=0
RESB=0
RESB=1
8c. Wait for Interrupt i
WAI
1 OpCode, 1 byte, 3 cycles
IRQB NMIB
(4)
9a. Relative r
BCC, BCS, BEQ, BMI, BNE, BPL,
BRA, BVC, BVS
9 OpCodes, 2 bytes, 2,3 and 4 cycles
9b. Relative Bit Branch r
BBRx, BBSx
16 OpCodes, 3 bytes, 5,6 and 7 cycles
(2)
(3)
(2)
(3)
1
2
3
4
5
1
2
3
4
5
6
7
1
1
2
3
4
5
6
7
1
1
2
3
4
5
6
1
1
2
3
4
5
6
1
1
2
3
1
1
2
3
4
1
1
2
3
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
PC
PC+1
0,zp
PC+2
PC+Offset
PC
PC
01,S
01,S-1
01,S-2
VA
VA+1
New PC
PC
PC+1
S
S-1
S-2
VA
VA+1
New PC
PC
PC+1
S+1
S+2
S+3
PC+1
Return PC
PC
PC+1
PC+1
S+1
S+2
PC+1
Return PC
PC
PC+1
S
PC+1
PC
PC+1
PC+1
S+1
PC+1
PC
PC+1
0,zp
PC+2
OpCode
zp
Data
Offset
New OpCode
not used
not used
Return PCH
Return PCL
Return P
New PCL
New PCH
New OpCode
OpCode
not used
Return PCH
Return PCL+2
Return P
New PCL
New PCH
New OpCode
OpCode
Not Used
Return P
Return PCL
Return PCH
IO
New OpCode
OpCode
not used
not used
Return PCL
Return PCH
IO
New OpCode
OpCode
not used
Register Value
New OpCode
OpCode
not used
not used
Register Value
New OpCode
OpCode
zp
Data
New OpCode
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1/0
1
10a. Stack s
ABORTB, IRQB, NMIB, RESB
4 hardware interrupts, 0 bytes, 7 cycles
(5)
10b. Stack (Software Interrupts) s
BRK
1 OpCode, 2 bytes, 7 cycles
10c. Stack (Return from interrupt) s
RTI
1 OpCode, 1 byte, 6 cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
10d. Stack (Return from subroutine) s
RTS
1 OpCode, 1 byte, 6 cycles
10e. Stack s
PHA, PHP, PHX, PHY
4 OpCodes, 1 byte, 3 cycles
10f. Stack s
PLA, PLP, PLX, PLY
4 OpCodes, 1 byte, 4 cycles
11a. Zero Page zp
ADC, AND, BIT, CMP, CPX, CPY,
EOR, LDA, LDX, LDY, ORA, SBC,
STA, STX, STY, STZ
16 OpCodes, 2 bytes, 3 and 4 cycles