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參數資料
| 型號： | W58105 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 音頻合成 |
| 英文描述： | ADPCM Voice Synthesizer(ADPCM話音合成器) |
| 中文描述： | 20 SEC, SPEECH SYNTHESIZER, UUC16 |
| 文件頁數： | 20/41頁 |
| 文件大小： | 195K |
| 代理商： | W58105 |
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W581xx Design Guide
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20 -
1. Tdeb means the "Debounce time" which can be "Long" or "Short", depending on bit4 of the MODE
register. If the MODE register has a "1" in bit4, then the debounce time will be set to "Long" If bit4 is
"0",” then the debounce time will be set to "Short". In case of last synthesized speech sampling rate
is 6kHz, for long debounce Tdeb = 256/6k = 42.7ms, for short debounce Tdeb = 2/6k = 333us.
2. Only when Tclr is longer than Tdeb, the receiving data counter of W581xx can be clear to zero.
Considering about the speech sampling frequency may shift due to the deviation of component or
voltage, at least 20% mark up,i.e. 42.7ms * (1 + 20%) = 51.2 ms for long debounce when the last
synthesized speech sampling rate is 6kHz, is suggested to guarantee the success of debounce.
For short debounce at 6kHz speech sampling rate, 333us * (1 + 20%) = 400 us were recommended.
3. Tcrd is the "CPU Reset Delay" time.
4. During data transfer phase, Tzero, the consecutive low state on TG1(data), could not be longer
than half of debounce time Tdeb, otherwise it may be treated as a debounce and then reset the
receiving data counter. For the same reason of possible frequency shift just like Tclr, 20% margin
were suggested. At Fs = 6kHz and long debounce, the consecutive low state on TG1(Tzero) can not
more than 0.5 * Tdeb * (1 - 20%) = 0.5 * 42.7 ms * 0.8 = 17 ms for long debounce and 0.5 * 333us *
(1-20%) = 133 us for short debounce.
To program W581XX in CPU
mode, the
CPU
keyword must be added and TG1F/ TG1R/ TG2F/
TG2R must be disabled including the directly interrupt and condition commands. So In the CPU
mode the "@TG1_high/low" and "@TG2_high/low" are illegal and bit0, bit1, bit4 and bit5 of the EN
register must be set to "0". The following example shows this: (for reference only)
W58105
CPU
LED1_S_CTL
LED2_STC_CTL
; Reserved word, for CPU mode mask option
32:
LD EN,0X0C
LD MODE,0X8F
; disable TG1F/TG1R/TG2F/TG2R
; bit4 of the MODE register is 0
; so the debounce time is selected "Short" (arround 350
μ
S)
END
0:
1:
4:
5:
END
162:
; CPU interrupt
H4+voice1+T4
END
The waveform must be sent from the external
μ
C through TG1 and TG2 to control the playing of the
voice group. The waveform looks like this:
In the program example (for reference only) shown above, the
μ
C will transfer the number 162 to
interrupt W581XX. The number 162 (decimal) is equal to 10100010b (binary).
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