
W53322/W53342
- 10 -
SRP
SR
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
SR Symbol
-----
-----
TM0L(w)
TM0H(w)
TM1L(w)
TM1H(w)
TMC1L(r)
TMC1H(r)
-----
-----
EVFL(r,c)
EVFH(r,c)
HEFL(r/w,s/c)
HEFH(r/w,s/c)
IEFL(r/w,s/c)
IEFH(r/w,s/c)
HCFL(r)
HCFH(r)
LDIV(w)
-----
PEFL(r/w,s/c)
PEFH(r/w,s/c)
RP0L(r/w)
RP0M(r/w)
RP1L(r/w)
RP1M(r/w)
RP0H(r/w)
RP1H(r/w)
MLDL(w)
MLDH(w)
SPCL(w)
SPCH(w)
CF(r,s/c)
-----
FLAG0(r/w,s/c)
Function
Bit 3 ~ 0 assignment
low nibble of Timer 0
high nibble of Timer 0
low nibble of Timer 1
high nibble of Timer 1
low nibble of Timer 1
high nibble of Timer 1
TM0.3~TM0.0
TM0.7~TM0.4
TM1.3~TM1.0
TM1.7~TM1.4
TM1.3~TM1.0
TM1.7~TM1.4
05H
Event Flag (set by chip hardware
if interrupt is occurred)
Hold mode release Enable Flag
RD,RC,TM0,DIV
TM1,SPEECH,MELODY,X
RD,RC,TM0,DIV
TM1,SPEECH,MELODY,X
RD,RC,TM0,DIV
TM1,SPEECH,MELODY,X
RD,RC,TM0,DIV
TM1,SPEECH,MELODY,X
LDIV.3 ~ LDIV.0
06H
07H
Interrup Enable Flag
Hold mode release Condition Flag
(set by H/W if hold mode is released)
Divider of LCD fundamental frequency
Port Enable Flag for hold mode
release or interrupt function
RAM address Pointer 0 Low nibble
RAM address Pointer 0 Middle nibble
RAM address Pointer 1 Low nibble
RAM address Pointer 1 Middle nobble
RAM address Pointer 0 High nibble
RAM address Pointer 1 High nibble
MeLoDy score address Low nibble
MeLoDy score address High nibble
SPeeCh section address Low nibbel
SPeeCh section address High nibbel
Carrier Flag
RC.3, RC.2, RC.1, RC.0
RD.3, RD.2, RD.1, RD.0
RP0.3~RP0.0
RP0.7~RP0.4
RP1.3~RP1.0
RP1.7~RP1.4
X,X, RP0.9,RP0.8
X,X, RP1.9,RP1.8
MLD.3~MLD.0
MLED1,MLED0, OSB,MLD.4
SPC.3~SPC.0
SPC.7~SPC.4
X,X,X,CF
melody/speech busy and play flag
MLD_busy,SPC_busy,MLD_play,
SPC_play
X,DIVR,WDTR,X
23
24
25
FLAG1(c)
-----
-----
reset flag for Divider/WatchDog