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參數資料
| 型號： | W523S08 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 音頻合成 |
| 英文描述： | HIGH FIDELITY PowerSpeech-TM |
| 中文描述： | 8 SEC, SPEECH SYNTHESIZER, UUC19 |
| 文件頁數： | 7/14頁 |
| 文件大小： | 90K |
| 代理商： | W523S08 |
W523SXX
(PRELIMINARY)
Publication Release Date: Oct 2000
- 7 -
Revision A5
Interrupt Vector Allocation
The W523Sxx provides a total of 4 trigger inputs to communicate with the outside world. Each trigger
pin can invoke 2 dedicate interrupt vectors depending on TG pins’ status (rising or falling). The table
below shows the relationship between triggers’ status and interrupt vectors.
INTERRUPT VECTOR
0
1
8
9
TRIGGER SOURCE
TG1F
TG2F
TG5F
TG6F
INTERRUPT VECTOR
4
5
12
13
32
TRIGGER SOURCE
TG1R
TG2R
TG5R
TG6R
POI
CPU Interface
The W523Sxx can communicate with an external microprocessor through a simple serial CPU
interface. The CPU interface consists of TG1, TG2 and STPA/BUSY pins, which are shown below:
Debounced OK. to clear the internal CPU
counter for preventing the system from
running away. (TG1F should be disabled.)
T
DEB
END
T
CRD
TG1
(Data)
TG2
(Clock)
STPA/Busy
AUD/SPK+
Note:
1. T
DEB
means the "Debounce time".
2. T
CRD
is the "CPU Reset Delay" time. This should be more than 2.6
μ
S.
3. The "Clock" frequency of the TG2 pin can be set in the range: 10 KHz - 1 MHz.
Busy signal will output "high" after the end of transmission. The rising timing of Busy signal is
相關PDF資料 |
PDF描述 |
|---|---|
| W523S10 | HIGH FIDELITY PowerSpeech-TM |
| W523S12 | HIGH FIDELITY PowerSpeech-TM |
| W523S15 | HIGH FIDELITY PowerSpeech-TM |
| W523S20 | HIGH FIDELITY PowerSpeech-TM |
| W523S25 | HIGH FIDELITY PowerSpeech-TM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W523S10 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY PowerSpeech-TM |
| W523S12 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY PowerSpeech-TM |
| W523S15 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY PowerSpeech-TM |
| W523S20 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY PowerSpeech-TM |
| W523S25 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY PowerSpeech-TM |
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