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參數資料
| 型號： | W523A080 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 音頻合成 |
| 英文描述： | HIGH FIDELITY POWER SPEECH |
| 中文描述： | 80 SEC, SPEECH SYNTHESIZER, UUC29 |
| 封裝： | DIE-29 |
| 文件頁數： | 10/19頁 |
| 文件大小： | 775K |
| 代理商： | W523A080 |
W523AXXX
- 10 -
5.4 CPU Interface
The W523Axxx can communicate with an external microprocessor through a simple serial CPU
interface. The CPU interface consists of TG1, TG2 and STPA/BUSY pins, which are shown below:
Debounced OK. to clear the internal CPU
counter for preventing the system from
running away. (TG1F should be disabled.)
T
DEB
END
T
CRD
TG1
(Data)
TG2
(Clock)
STPA/Busy
AUD/SPK+
Notes:
1. T
DEB
means the "Debounce time".
2. T
CRD
is the "CPU Reset Delay" time. This should be more than 2.6
μ
S.
3. The "Clock" frequency of the TG2 pin can be set in the range: 10 KHz - 1 MHz.
Busy signal will output "high" after the end of transmission. The rising timing of Busy signal is
dependent on the MSB of data output on TG1 (Data) pin. If MSB is "1", Busy will rise after the last
rising edge of TG2 (Clock) pin. If MSB is "0", Busy will rise after the rising edge that TG1 (Data)
returns to high.
TG1
(DATA)
TG2
(CLK)
BUSY
7 bits
MSB=0
40ns
TG1
(DATA)
TG2
(CLK)
BUSY
7 bits
MSB=1
40ns
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| W523A120 | HIGH FIDELITY POWER SPEECH |
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相關代理商/技術參數 |
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|---|---|
| W523A100 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY POWER SPEECH |
| W523A120 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY POWER SPEECH |
| W523AXXX | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY POWER SPEECH |
| W523M02 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY PowerSpeech-TM |
| W523S08 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:HIGH FIDELITY PowerSpeech-TM |
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