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參數(shù)資料
型號(hào)： W48S87-04
廠商： IC WORKS INC
元件分類： XO, clock
英文描述： Spread Spectrum 3 DIMM Desktop Clock(寬頻譜3 DIMM桌上型PC機(jī)時(shí)鐘)
中文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO48
文件頁(yè)數(shù)： 17/21頁(yè)
文件大?。?/td> 200K
代理商： W48S87-04
W48S87-04
PRELIMINARY
17
3.3V AC Electrical Characteristics
(CPU3.3#_2.5 Input = 0)
(continued)
SDRAM Clock Outputs, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
Parameter
t
P
f
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
CPU = 66.8 MHz
CPU = 60 MHz
Unit
ns
Min.
15
Typ.
Max.
Min.
16.7
Typ.
Max.
Frequency, Actual
Determined by PLL divider ratio
66.8
59.876
MHz
t
R
t
F
t
D
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
1
4
V/ns
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
1
4
V/ns
Duty Cycle
Measured on rising and falling edge at
1.5V
45
55
45
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Max-
imum difference of cycle time between
two adjacent cycles.
250
250
ps
t
SK
t
SK
Output Skew
Measured on rising edge at 1.5V
100
100
ps
CPU to SDRAM Clock
Skew
Covers all CPU/SDRAM outputs. Mea-
sured on rising edge at 1.5V.
500
500
ps
f
ST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cy-
cles exist prior to frequency stabiliza-
tion.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series ter-
mination value.
10
15
20
10
15
20
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF)
Parameter
t
P
f
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
CPU = 66.8 MHz
CPU = 60 MHz
Unit
ns
Min.
30
Typ.
Max.
Min.
33.3
Typ.
Max.
Frequency, Actual
Determined by PLL divider ratio
33.4
29.938
MHz
t
H
t
L
t
R
t
F
t
D
High Time
Duration of clock cycle above 2.4V
12
13.3
ns
Low Time
Duration of clock cycle below 0.4V
12
13.3
ns
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
1
4
V/ns
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
1
4
V/ns
Duty Cycle
Measured on rising and falling edge at
1.5V
45
55
45
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Max-
imum difference of cycle time between
two adjacent cycles.
250
250
ps
t
SK
t
O
Output Skew
Measured on rising edge at 1.5V
250
250
ps
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Mea-
sured on rising edge at 1.5V. CPU
leads PCI output.
1
4
1
4
ns
f
ST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cy-
cles exist prior to frequency stabiliza-
tion.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
15
20
30
15
20
30
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PDF描述
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