
W48S101-04
PRELIMINARY
2
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
CPU0:3
40, 39, 36,
35
O
CPU Clock Outputs 0 through 3:
These four CPU clock outputs are controlled by
the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.
PCI1:7
8, 10, 11,
13, 14, 16,
17
O
PCI Bus Clock Outputs 1 through 7:
These seven PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F
7
O
Fixed PCI Clock Output:
Unlike PCI1:7 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
CPU_STOP# Input:
When brought LOW, clock outputs CPU0:3 are stopped LOW
after completing a full clock cycle (2
–
3 CPU clock latency). When brought HIGH,
clock outputs CPU0:3 start beginning with a full clock cycle (2
–
3 CPU clock latency).
PCI_STOP# Input:
The PCI_STOP# input enables the PCI 1:7 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
SPREAD# Input:
When brought LOW this pin activates Spread Spectrum clocking.
CPU_STOP#
30
I
PCI_STOP#
31
I
SPREAD#
28
I
APIC0:1
45, 44
O
I/O APIC Clock Outputs:
Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.
48MHz
22
O
48-MHz Output:
Fixed clock outputs at 48 MHz. Output voltage swing is controlled
by voltage applied to VDDQ3.
24-MHz or 48-MHz Output:
24-MHz output when pin 1 is strapped through 10-k
resistor to VDDQ3. 48-MHz output when pin 1 is strapped through 10-k
resistor to
GND.
24/48MHz
23
O
REF0/SEL48#
1
I/O
I/O Dual Function REF0 and SEL48# pin:
During power on, SEL48# input will be
latched, which will set pin 23 to output 24 MHz or 48 MHz. It then reverts to REF0
fixed output.
REF1:2
2, 47
O
Fixed 14.318-MHz Outputs 1 through 2:
Used for various system applications.
Output voltage swing is controlled by voltage applied to VDDQ3.
SEL100/66#
25
I
Frequency Selection Input:
Selects power-up default CPU clock frequency as
shown in
Table 1
on page 1.
Clock pin for I
2
C circuitry.
Data pin for I
2
C circuitry.
Crystal Connection or External Reference Frequency Input:
This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
SCLK
26
I
SDATA
27
I/O
X1
4
I
X2
5
I
Crystal Connection:
An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Down Control:
When this input is LOW, device goes into a low-power stand-
by condition. All outputs are actively held LOW while in power-down. CPU and PCI
clock outputs are stopped LOW after completing a full clock cycle (2
–
3 CPU clock
cycle latency). When brought HIGH, CPU, SDRAM and PCI outputs start with a full
clock cycle at full operating frequency (3 ms maximum latency).
Power Connection:
Connect to 3.3V supply.
PWR_DWN#
29
I
VDDQ3
9, 15, 19,
21, 33, 48
P
VDDQ2
46, 41, 37
P
Power Connection:
Power supply for APIC0:1 and CPU0:3 output buffers. Connect
to 2.5V.
GND
3, 6, 12, 18,
20, 24, 32,
34, 38, 43
G
Ground Connections:
Connect all ground pins to the common system ground
plane.