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參數資料
| 型號： | W48C111-17 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 100-MHz Mobile Motherboard System Clock(100-MHz 移動主板系統時鐘) |
| 中文描述： | 100兆赫移動主板的系統時鐘（100兆赫移動主板系統時鐘） |
| 文件頁數： | 2/7頁 |
| 文件大?。?/td> | 114K |
| 代理商： | W48C111-17 |
W48C111-17
PRELIMINARY
2
Pin Definitions
Pin Name
CPU0:1
Pin
No.
24, 23
Pin
Type
O
Pin Description
CPU Clock Outputs 0 and 1:
These two CPU clock outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ2. Frequency of signals is set by SEL100/66# input.
PCI1:5
5, 7, 8, 10,
11
O
PCI Bus Clock Outputs 1 through 5:
These five PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F
4
O
Fixed PCI Clock Output:
Unlike PCI1:5 outputs, this output is not controlled by the
PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage
swing is controlled by voltage applied to VDDQ3.
48MHz
16
O
48-MHz Output:
Fixed clock output at 48 MHz. Output voltage swing is controlled by
voltage applied to VDDQ3.
CPU_STOP#
18
I
CPU_STOP# Input:
When brought LOW, clock outputs CPU0:1 are stopped LOW
after completing a full clock cycle (2
–
3 CPU clock latency). When brought HIGH,
clock outputs CPU0:1 start with a full clock cycle (2
–
3 CPU clock latency).
PCI_STOP#
19
I
PCI_STOP# Input:
The PCI_STOP# input enables the PCI1:5 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
Fixed 14.318-MHz Output:
Used for various system applications. Output voltage
swing is controlled by voltage applied to VDDQ3.
REF
26
O
SEL100/66#
15
I
Frequency Selection Inputs:
Select power-up default CPU clock frequency as
shown in
Table 1
on page 1.
X1
1
I
Crystal Connection or External Reference Frequency Input:
This pin can either
be used as a connection to a crystal or to a reference signal.
X2
2
I
Crystal Connection:
An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power-Down Control:
When this input is LOW, device goes into a low-power stand-
by condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW
after completing a full clock cycle (2
–
3 CPU clock cycle latency). When brought
HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
Power Connection:
Connected to 3.3V supply.
PWR_DWN#
17
I
VDDQ3
6, 9, 13, 21,
27
P
VDDQ2
25
P
Power Connection:
Power supply for CPU0:1 output buffer. Connected to 2.5V.
Ground Connection:
Connect all ground pins to the common system ground plane.
GND
3, 12, 14, 20,
22, 28
G
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