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參數(shù)資料
| 型號： | W48C111-16 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Frequency Generator for Integrated Core Logic(在集成核心邏輯中應(yīng)用的頻率發(fā)生器) |
| 中文描述： | 頻率發(fā)生器集成的核心邏輯（在集成核心邏輯中應(yīng)用的頻率發(fā)生器） |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 114K |
| 代理商： | W48C111-16 |
W48C111-16
PRELIMINARY
5
AC Electrical Characteristics
T
A
= 0
°
C to +70
°
C, V
DDQ3
= 3.3V±5%,V
DDQ2
= 2.5V
±
5%, f
XTL
= 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
Description
Period
Test Condition/Comments
Measured on rising edge at 1.25V
CPU = 66.6 MHz
CPU = 100 MHz
Unit
ns
Min.
15
Typ.
Max.
15.5
Min.
10
Typ.
Max.
10.5
High Time
Duration of clock cycle above 2.0V
5.2
3.0
ns
Low Time
Duration of clock cycle below 0.4V
5.0
2.8
ns
Output Rise Time
Measured from 0.4V to 2.0V
0.4
1.6
0.4
1.6
V/ns
Output Fall Time
Measured from 2.0V to 0.4V
0.4
1.6
0.4
1.6
V/ns
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
200
250
ps
t
SK
f
ST
Output Skew
Measured on rising edge at 1.25V
175
175
ps
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
13.5
13.5
PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
Description
Test Condition/Comments
Measured on rising edge at 1.5V
CPU = 66.6/100 MHz
Unit
ns
Min.
30
Typ.
Max.
Period
High Time
Duration of clock cycle above 2.4V
12
ns
Low Time
Duration of clock cycle below 0.4V
12
ns
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
250
ps
t
SK
t
O
Output Skew
Measured on rising edge at 1.5V
500
ps
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1.5
4
ns
f
ST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
30
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W48C111-16H | 功能描述:IC CLOCK GEN FREQ MOD 28-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| W48C111-16HT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| W48C111-17 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Mobile Motherboard System Clock |
| W48C20 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Audio Subsystem Clock Generator |
| W48C20-08G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Miscellaneous Clock Generator |
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