
W48C101-01
PRELIMINARY
6
PCI Clock Outputs, PCI1:7 and PCI_F (Lump Capacitance Test Load = 30 pF
Parameter
Description
Test Condition/Comments
CPU = 66.6/100 MHz
Min.
Typ.
Unit
Max.
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
Period
Measured on rising edge at 1.5V
30
ns
High Time
Duration of clock cycle above 2.4V
12
Low Time
Duration of clock cycle below 0.4V
12
ns
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
250
ps
t
SK
t
O
Output Skew
Measured on rising edge at 1.5V
500
ps
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1.5
4
ns
f
ST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
15
APIC0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
f
t
R
t
F
t
D
f
ST
Description
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Measured from 2.0V to 0.4V
Measured on rising and falling edge at 1.25V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6/100MHz
Min.
Typ.
14.31818
1
1
45
Unit
MHz
V/ns
V/ns
%
ms
Max.
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
4
4
55
1.5
Z
o
AC Output Impedance
15
REF0:2 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
f
Description
Test Condition/Comments
Frequency generated by crystal oscillator
CPU = 66.6/100 MHz
Unit
MHz
Min.
Typ.
14.318
Max.
Frequency, Actual
t
R
t
F
t
D
f
ST
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
25