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參數資料
| 型號： | W40S01-04 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Low-voltage, Eighteen-Output Signal Buffer(低電壓18個輸出端信號緩沖器（適合于驅動靜態DRAM- 4 雙列直插存儲器模塊(DIMM）)) |
| 中文描述： | 低電壓，18輸出信號緩沖（低電壓18個輸出端信號緩沖器（適合于驅動靜態內存- 4雙列直插存儲器模塊（DIMM）的）） |
| 文件頁數： | 6/10頁 |
| 文件大小： | 128K |
| 代理商： | W40S01-04 |
W40S01-04
6
Signaling Requirements
As shown in
Figure 2
, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a
“
start bit
”
as shown in
Figure
3
. A
“
stop bit
”
signifies that a transmission has ended.
As stated previously, the W40S01-04 sends an
“
acknowledge
”
pulse after receiving eight data bits in each byte as shown in
Figure 4
.
Sending Data to the W40S01-04
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double buff-
ered). Partial transmission is allowed meaning that a transmis-
sion can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Transmis-
sion is truncated with either a stop bit or new start bit (restart
condition).
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 2. Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Start
Bit
Stop
Bit
Figure 3. Serial Data Bus Start and Stop Bit
相關PDF資料 |
PDF描述 |
|---|---|
| W40S01 | SDRAM Buffer - 4 DIMM |
| W40S11-02 | Low-voltage, Ten-output Clock Buffer(低電壓10輸出時鐘緩沖器（適合于驅動靜態DRAM- 雙列直插存儲器模塊(DIMM）) |
| W40S11-03 | Low-voltage, 14-output Buffer(低電壓14輸出緩沖器（適合于驅動靜態DRAM- 雙列直插存儲器模塊(DIMM）) |
| W40S11-23 | Clock Buffer/Driver(時鐘緩沖器/驅動器) |
| W40S11 | SDRAM Buffer - 2 DIMM (Mobile) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W40S01-04H | 功能描述:IC CLK BUFF 18OUT SDRAM 48SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| W40S01-04HT | 制造商:Cypress Semiconductor 功能描述: |
| W40S11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Buffer/Driver |
| W40S11-02 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:SDRAM Buffer - 2 DIMM (Mobile) |
| W40S11-02H | 功能描述:IC CLK BUFF 10OUT SDRAM 28SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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