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參數資料
| 型號： | W40C06A |
| 廠商： | IC WORKS INC |
| 元件分類： | XO, clock |
| 英文描述： | Six Outputs low-skew clock buffer(六輸出低斜率的時鐘緩沖器) |
| 中文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO16 |
| 文件頁數： | 2/6頁 |
| 文件大小： | 108K |
| 代理商： | W40C06A |
W40C06A
2
General Overview
The W40C06A is a six-output, low-skew clock buffer ideally
suited for PCI, CPU, and other system clock applications. Each
high-current, low-impedance output is specifically designed to
drive up to two impedance-controlled signal lines. Controlled
output rise/fall times further help to provide good signal char-
acteristics.
The W40C06A is ideal for clock signal distribution in skew sen-
sitive applications such as Pentium
processor or PCI appli-
cations. W40C06A-14 has an enable input pin (see
Table 1
)
that starts and stops the clock outputs without producing short
cycles.
Functional Description
The W40C06A enable pin provides start/stop control of buffer
outputs Q0 through Q5. Refer to
Table 1
,
“
Output Enable Se-
lection,
”
for decoding. Active (enabled) outputs are in phase
with TCLK but are phase delayed by several nanoseconds.
Low (disabled) outputs are held at logic LOW.
Synchronization Logic
Output Control
To prevent output
“
short cycling,
”
internal synchronization logic
is used to ensure complete clocks cycles. This is true for both
output enable or disable. Upon enabling an output, there is a
maximum latency of four clock cycles, assuming the crystal
oscillator is active.
Clock Transmission Lines in System Applications
With the increase in system clock frequencies, transmission
line theory is commonly being applied to the design of clock
distribution lines. High-speed logic systems typically require
tight skew control between clock lines, which means that the
clock signal must have short rise/fall times to overcome the
effect of noise. Short rise/fall times may create other problems
such as signal overshoot/undershoot and signal reflections
which may result in distorting the signal at the load end. These
problems must be avoided since they create unwanted clock
skew.
Reflections and signal overshoot/undershoot can be con-
trolled by designing clock distribution traces as transmission
lines. A transmission line accepts and delivers a clock signal
without distortion or reflections if its impedance is matched to
the line source and load. In system clock line implementation,
source impedance is typically controlled but is not practical to
control load impedance.
Clock source impedance is matched to the transmission line
by using series termination; this involves the addition of a se-
ries termination resistor between the output pin and transmis-
sion line to, in effect, raise the output buffer impedance to
match the line. For example, if the clock output buffer imped-
ance is 30
and the transmission line impedance is 50
, a
20
termination resistor connected between the clock output
and transmission line will match the two (the clock buffer im-
pedance becomes 50
).
The end of the transmission line is usually
“
open
”
with the only
load being the typically high-resistance capacitive load of the
logic input on the device being clocked. This condition causes
a reflection to be sent back to the source. If the source is prop-
erly matched to line (through series termination), this reflection
will be absorbed (a poorly matched source will re-reflect the
pulse edge which can cause waveform distortion by mixing a
reflected edge with a new clock pulse edge).
It is interesting to note that when a new clock edge is first
driven into the transmission line, the voltage level at the input
of the line is only one-half the final signal amplitude, assuming
a properly matched line. This edge remains at half amplitude
for the time it takes for the edge to reach the end of the line
and back. The edge travels down the line at a speed of about
0.2 ns per inch of transmission, so for a five-inch line this
round-trip takes about 2.0 ns. During that time, the clock
source dissipates power at the rate of (V
DD
/2)
2
/R, where R is
the sum resistance of the output buffer and series termination
resistor (this assumes the case of a CMOS output driver, as
used in the W40C06A, where the clock signal amplitude is
equal to V
DD
).
W40C06A Clock Driver Advantages
Low Output Impedance
The typical CMOS clock buffer device has an output imped-
ance of around 50
. This means that a typical 60
transmis-
sion line can be properly series terminated with a 10
match-
ing resistor. However, two 60
transmission lines could not be
driven with series termination (to maintain good waveform in-
tegrity) since this presents a 30
load to the buffer.
The W40C06A exhibits a 5
typical buffer output impedance.
The main advantage of the low W40C06A output impedance
is that one output can drive more than one transmission line
while maintaining proper series termination. For example, if
Pin Definitions
Pin Name
Q0:5
Pin
No.
4, 6, 8,
10, 12, 14
Pin
Type
O
Pin Description
Buffered Clock Outputs:
Six skew controlled CMOS clock outputs.
VDD
5, 9, 13
P
Power Connection:
Power supply for core logic and output buffers. Connected to a
3.3V supply.
Ground Connection:
Connect all ground pins to the common system ground plane.
GND
3, 7, 11
G
CKEN
2
I
Clock Enable:
Provide Start/Stop control of buffer outputs refer to
Table 1
.
Clock Input:
External reference frequency input.
TCLK
15
I
NC
1, 16
NC
No Connection:
These pins should remain unconnected.
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