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參數資料
| 型號： | W3H64M72E-533SBC |
| 英文描述： | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 64米× 72 DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁數： | 16/30頁 |
| 文件大小： | 956K |
| 代理商： | W3H64M72E-533SBC |
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W3H64M72E-XSBX
16
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
Function
CKE
CS#
RAS#
CAS#
WE#
BA2
BA1
BA0
A12
A11
A10
A9-A0
Notes
Previous
Cycle
H
H
H
Current
Cycle
H
H
L
LOAD MODE
REFRESH
SELF-REFRESH Entry
L
L
L
H
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
X
H
H
H
H
L
H
H
X
H
L
L
L
BA
X
X
OP Code
X
X
2
X
X
X
X
SELF-REFRESH Exit
L
H
X
X
X
X
7
Single bank precharge
All banks PRECHARGE
Bank activate
H
H
H
H
H
H
X
X
BA
X
X
L
H
X
X
2
Row Address
WRITE
H
H
L
L
H
L
BA
Column
Address
Column
Address
Column
Address
Column
Address
X
X
L
Column
Address
Column
Address
Column
Address
Column
Address
X
X
2, 3
WRITE with auto precharge
H
H
L
H
L
L
BA
H
2, 3
READ
H
H
L
H
L
H
BA
L
2, 3
READ with auto precharge
H
H
L
H
L
H
BA
H
2, 3
NO OPERATION
Device DESELECT
H
H
X
X
L
H
H
L
H
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
POWER-DOWN entry
H
L
X
X
X
X
4
POWER-DOWN exit
L
H
X
X
X
X
4
Note: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC
parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. X” means “H or L” (but a defined logic level).
7. Self refresh exit is asynchronous.
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| W3H64M72E-533SBI | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667ES | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667ESC | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667ESI | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W3H64M72E-533SBI | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H64M72E-533SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA MIL-TEMP. - Bulk |
| W3H64M72E-667ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667ESI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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