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參數(shù)資料
| 型號： | W3H64M72E-533ESM |
| 英文描述： | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 64米× 72 DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁數(shù)： | 15/30頁 |
| 文件大小： | 956K |
| 代理商： | W3H64M72E-533ESM |
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W3H64M72E-XSBX
15
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
EXTENDED MODE REGISTER 2
The extended mode register 2 (EMR2) controls functions
beyond those controlled by the mode register. Currently
all bits in EMR2 are reserved, as shown in Figure 8. The
EMR2 is programmed via the LM command and will
retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is
performed correctly.
Bit E7 (A7) must be programmed as"1" to provide a faster
refresh rate on devices if the T
CASE
exceeds 85°C
EMR2 must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time
t
MRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecified operation.
EXTENDED MODE REGISTER 3
The extended mode register 3 (EMR3) controls functions
beyond those controlled by the mode register. Currently,
all bits in EMR3 are reserved, as shown in Figure 9.
The EMR3 is programmed via the LM command and will
retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is
performed correctly.
EMR3 must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time
t
MRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecified operation.
COMMAND TRUTH TABLES
The following tables provide a quick reference of DDR2
SDRAM available commands, including CKE power-down
modes, and bank-to-bank commands.
FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
A9
A7 A 6 A5 A4 A3
A8
A2
A1 A0
Exten ded Mo de
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
0
1
A10
A12
A11
BA0
BA1
10
0
1
11
0
1
12
0
1
13
0
1
14
15
A13
0
1
0
1
Mode Register Definition
M15
0
0
1
1
M14
EMR3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BA2
16
M16
0
0
0
0
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Note: 1. E13 (A13)-E0 (A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
相關PDF資料 |
PDF描述 |
|---|---|
| W3H64M72E-533SB | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBI | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-667ES | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3H64M72E-533SB | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
| W3H64M72E-533SBI | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H64M72E-533SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA MIL-TEMP. - Bulk |
| W3H64M72E-667ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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