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參數(shù)資料
| 型號： | W3H64M72E-400SBI |
| 英文描述： | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 中文描述： | 64米× 72 DDR2 SDRAM的208 PBGA封裝多芯片封裝 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大小： | 956K |
| 代理商： | W3H64M72E-400SBI |
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W3H64M72E-XSBX
18
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
March 2006
Rev. 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
READ COMMAND
The READ command is used to initiate a burst read access
to an active row. The value on the BA2–BA0 inputs selects
the bank, and the address provided on inputs A0–i (where
i = A9) selects the starting column location. The value on
input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed
will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
READ OPERATION
READ bursts are initiated with a READ command. The
starting column and bank addresses are provided with the
READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled,
the row being accessed is automatically precharged at the
completion of the burst. If auto precharge is disabled, the
row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the
starting column address will be available READ latency
(RL) clocks later. RL is defined as the sum of AL and CL;
RL = AL + CL. The value for AL and CL are programmable
via the MR and EMR commands, respectively. Each
subsequent data-out element will be valid nominally at
the next positive or negative clock edge (i.e., at the next
crossing of CK and CK#).
DQS/DQS# is driven by the DDR2 SDRAM along with
output data. The initial LOW state on DQS and HIGH state
on DQS# is known as the read preamble (
t
RPRE). The
LOW state on DQS and HIGH state on DQS# coincident
with the last data-out element is known as the read
postamble (
t
RPST).
Upon completion of a burst, assuming no other commands
have been initiated, the DQ will go High-Z.
Data from any READ burst may be concatenated with
data from a subsequent READ command to provide a
continuous flow of data. The first data element from the
new burst follows the last element of a completed burst.
The new READ command should be issued
x
cycles after
the first READ command, where
x
equals BL / 2 cycles.
FIGURE 11 – READ COMMAND
DON’T CARE
CK
CK#
CS#
RAS#
CAS#
WE#
CKE
Col
Bank
ADDRESS
BANK ADDRESS
AUTO PRECHARGE
ENABLE
A10
DISABLE
相關PDF資料 |
PDF描述 |
|---|---|
| W3H64M72E-400SBM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ES | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESC | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESI | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESM | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3H64M72E-400SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 400MHZ, 208PBGA MIL-TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H64M72E-533ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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