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參數資料
| 型號： | W3EG7266S265BD4 |
| 英文描述： | 512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| 中文描述： | 512MB的- 64Mx72 DDR SDRAM的無緩沖ECC瓦特/鎖相環 |
| 文件頁數： | 9/13頁 |
| 文件大小： | 203K |
| 代理商： | W3EG7266S265BD4 |
W3EG7266S-AD4
-BD4
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
October 2004
Rev. 7
PRELIMINARY
Notes
1.
2.
All voltages referenced to V
SS
.
Tests for AC timing, I
DD
, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specifications
and device operation are guaranteed for the full voltage range specified.
Outputs measured with equivalent load:
3.
Output
(V
OUT
)
Reference
Point
30pF
50
V
TT
4.
AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 1.5V in the test
environment, but input timing is still referenced to V
REF
(or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The mini-mum slew rate for the input signals
used to test the device is 1V/ns in the range between V
IL
(AC) and V
IH
(AC).
The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
V
REF
is expected to equal V
CCQ/2
of the transmitting device and to track variations
in the DC level of the same. Peak-to-peak noise (non-common mode) on V
REF
may
not exceed ±2 percent of the DC value. Thus, from V
CCQ/2
, V
REF
is allowed ±25mV
for DC error and an additional ±25mV for AC noise. This measurement is to be
taken at the nearest V
REF
bypass capacitor.
V
TT
is not applied directly to the device. V
TT
is a system supply for signal
termination resistors, is expected to be set equal to V
REF
and must track variations
in the DC level of V
REF
.
I
DD
is dependent on output loading and cycle rates. Specified values are obtained
with mini-mum cycle time at CL = 2 for 262 and 202, CL = 2.5 for 265, 335 and
CL = 3 for 403 with the outputs open.
Enables on-chip refresh and address counters.
10. I
DD
specifications are tested after the device is properly initialized, and is averaged
at the defined cycle rate.
11. This parameter is sampled. V
CC
= +2.5V ±0.2V, V
CCQ
= +2.5V ±0.2V, V
REF
= V
SS
, f
= 100 MHz, T
A
= 25°C, V
OUT
(DC) = V
CCQ/2
, V
OUT
(peak to peak) = 0.2V. DM input is
grouped with I/O pins, reflecting the fact that they are matched in loading.
12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing
must be derated: t
IS
has an additional 50ps per each 100 mV/ns reduction in slew
rate from 500 mV/ns, while t
IH
is unaffected. If the slew rate exceeds 4.5 V/ns,
functionality is uncertain. For 335, slew rates must be 0.5 V/ns.
13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
V
REF
.
14. Inputs are not recognized as valid until V
REF
stabilizes. Exception: during the period
before V
REF
stabilizes, CKE < 0.3 x V
CCQ
is recognized as LOW.
15. The output timing reference level, as measured at the timing reference point
indicated in Note 3, is V
TT
.
16. t
HZ
and t
LZ
transitions occur in the same access time windows as data valid
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
5.
6.
7.
8.
9.
17. The intent of the Don’t Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high [above V
IHDC
(MIN)] then it must not transition low (below
V
IHDC
) prior to t
DQSH
(MIN).
18. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on t
DQSS
.
20. MIN (t
RC
or t
RFC
) for I
DD
measurements is the smallest multiple of t
CK
that meets
the minimum absolute value for the respective parameter. t
RAS
(MAX) for I
DD
measurements is the largest multiple of t
CK
that meets the maximum absolute value
for t
RAS
.
21. The refresh period 64ms. This equates to an average refresh rate of 7.8125μs.
However, an AUTO REFRESH command must be as-serted at least once every
70.3μs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
22. The data valid window is derived by achieving other specifications: t
HP
(t
CK/2
), t
DQSQ
,
and t
QH
(t
QH
= t
HP
- t
QHS
). The data valid window derates directly porportional with
the clock duty cycle and a practical data valid window can be derived. The clock
is allowed a maximum duty cycle variation of 45/55, beyond which functionality is
uncertain.
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (t
RFC
[MIN]) else CKE is LOW (i.e., during
standby).
25. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, V
IL
(AC) or V
IH
(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, V
IL
(DC) or V
IH
(DC).
26. JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns
differentially).
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.
If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps
must be added to t
DS
and t
DH
for each 100 mV/ns reduction in slew rate. If slew rate
exceeds 4 V/ns, functionality is uncertain. For 403, slew rates must be ≥ 0.5 V/ns.
28. V
CC
must not vary more than 4 percent if CKE is not active while any bank is active.
29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary
by the same amount.
30. t
HP
min is the lesser of t
CL
minimum and t
CH
minimum actually applied to the device
CK and CK/ inputs, collectively during bank active.
31. READs and WRITEs with auto precharge are not allowed to be issued until
t
RAS
(MIN) can be satisfied prior to the internal precharge command being issued.
32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and
not more than +400mV or 2.9V maximum, whichever is less. Any negative glitch
must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V
mini-mum, whichever is more positive.
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| W3EG7266S265BD4I | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
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