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參數資料
| 型號： | W3EG7265S-JD3 |
| 英文描述： | 512MB - 2x32Mx72 DDR SDRAM REGISTERED, w/PLL |
| 中文描述： | 512MB的- 2x32Mx72 DDR SDRAM的注冊，瓦特/鎖相環 |
| 文件頁數： | 5/12頁 |
| 文件大小： | 208K |
| 代理商： | W3EG7265S-JD3 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7265S-JD3
PRELIMINARY
January 2005
Rev. 3
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
70°C, V
CC
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Operating Current
Symbol
I
DD0
Conditions
One device bank; Active - Precharge;
t
=t
(MIN); t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
One device bank; Active-Read-
Precharge Burst = 2; t
=t
(MIN);
t
=t
(MIN); l
= 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; t
CK
=t
CK
(MIN); CKE=(low)
DDR266@CL=2.0
Max
2025
DDR266@CL=2.5
Max
1980
DDR200@CL=2
Max
1980
Units
mA
Operating Current
I
DD1
2340
2295
2295
mA
Precharge Power-
Down Standby
Current
Idle Standby Current
I
DD2P
72
72
72
rnA
I
DD2F
CS# = High; All device banks idle;
t
=t
(MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. V
IN
= V
REF
for
DQ, DQS and DM.
One device bank active; Power-Down
mode; t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; t
=t
(MAX); t
=t
(MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
t
RC
= t
RC
(MIN)
810
810
810
mA
Active Power-Down
Standby Current
Active Standby
Current
I
DD3P
450
450
450
mA
I
DD3N
900
900
900
mA
Operating Current
I
DD4R
2250
2250
2250
mA
Operating Current
I
DD4W
2115
2115
2115
rnA
Auto Refresh
Current
Self Refresh Current
Operating Current
I
DD5
3015
3015
3015
mA
I
DD6
I
DD7A
CKE
≤
0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
=t
(MIN); t
=t
(MIN); Address and
control inputs change only during
Active Read or Write commands.
72
72
72
mA
mA
4050
4050
4050
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