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參數資料
| 型號： | W3EG7263S202JD3 |
| 英文描述： | 512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| 中文描述： | 512MB的，64Mx72 DDR SDRAM的注冊瓦特/鎖相環 |
| 文件頁數： | 7/13頁 |
| 文件大小： | 231K |
| 代理商： | W3EG7263S202JD3 |
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7263S-D3
-JD3
-AJD3
PRELIMINARY
April 2004
Rev. # 2
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ T
A
≤ +70°C; V
CC
= +2.5V ±0.2V, V
CCQ
= +2.5V ±0.2V
AC Characteristics
335
262/263/265
202
Parameter
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
Clock cycle time
Symbol
t
AC
t
CH
t
CL
t
CK
(2.5)
t
CK
(2)
t
DH
t
DS
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
DQSQ
t
DQSS
t
DSS
t
DSH
t
HP
t
HZ
t
LZ
t
IHf
t
ISf
t
IHs
t
ISs
t
IPW
t
MRD
t
QH
t
QHS
t
RAS
t
RAP
t
RC
t
RFC
Min
-0.7
0.45
0.45
6
7.5
0.45
0.45
1.75
-0.60
0.35
0.35
Max
+0.7
0.55
0.55
13
13
Min
-0.75
0.45
0.45
7.5
7.5/10
0.5
0.5
1.75
-0.75
0.35
0.35
Max
+0.75
0.55
0.55
13
13
Min
-0.8
0.45
0.45
8
10
0.6
0.6
2
-0.8
0.35
0.35
Max
+0.8
0.55
0.55
13
13
Units
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
16
16
22
22
CL=2.5
CL=2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
Address and control input hold time (fast slew rate)
Address and control input set-up time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
14,17
14,17
17
+0.60
+0.75
+0.8
0.35
1.25
0.5
1.25
0.6
1.25
13,14
0.75
0.2
0.2
0.75
0.2
0.2
0.75
0.2
0.2
t
CH
, t
CL
t
CH
, t
CL
t
CH
, t
CL
18
8,19
8,20
6
6
6
6
+0.70
+0.75
+0.8
-0.70
0.75
0.75
0.80
0.80
2.2
12
-0.75
0.90
0.90
1
1
2.2
15
-0.8
1.1
1.1
1.1
1.1
2.2
16
t
HP
-t
QHS
t
HP
-t
QHS
t
HP
-t
QHS
13,14
0.50
120,000
0.75
120,000
1
42
18
60
72
40
20
65
75
40
20
70
80
120,000
15
21
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W3EG7263S262AJD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S262D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S262JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S263AJD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S263D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
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