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參數(shù)資料
| 型號(hào)： | W3EG7263S202D3 |
| 英文描述： | 512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| 中文描述： | 512MB的，64Mx72 DDR SDRAM的注冊(cè)瓦特/鎖相環(huán) |
| 文件頁(yè)數(shù)： | 5/13頁(yè) |
| 文件大小： | 231K |
| 代理商： | W3EG7263S202D3 |
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5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7263S-D3
-JD3
-AJD3
PRELIMINARY
April 2004
Rev. # 2
I
DD
SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C
￡
T
A
￡
+70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V.
Includes DDR SDRAM components and PLL and Register
Parameter
Operating Current
Symbol
I
DD0
Rank 1
Conditions
One device bank; Active - Precharge;
t
= t
(MIN); t
= t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
One device bank; Active-Read-
Precharge Burst = 2; t
= t
(MIN);
t
= t
(MIN); l
= 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; t
CK
= t
CK
(MIN); CKE = (low)
CS# = High; All device banks idle;
t
= t
(MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. V
IN
= V
REF
for DQ, DQS
and DM.
One device bank active; Power-Down
mode; t
CK
(MIN); CKE = (low)
CS# = High; CKE = High; One device
bank; Active-Precharge;t
= t
(MAX); t
= t
(MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; t
CK
= t
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; t
= t
(MIN); DQ,DM and DQS
inputs changing once per clock cycle.
t
RC
= t
RC
(MIN)
DDR333@CL=2.5
Max
TBD
DDR266:@CL=2, 2.5
Max
1715
DDR200@CL=2 S
Max
1715
Units
mA
Rank 2
Standby
State
I
DD3N
Operating Current
I
DD1
TBD
2255
2255
mA
I
DD3N
Precharge Power-
Down Standby Current
Idle Standby Current
I
DD2P
TBD
54
54
rnA
I
DD2P
I
DD2F
TBD
671
671
mA
I
DD2F
Active Power-Down
Standby Current
Active Standby Current
I
DD3P
TBD
540
540
mA
I
DD3P
I
DD3N
TBD
1121
1121
mA
I
DD3N
Operating Current
I
DD4R
TBD
2795
2795
mA
I
DD3N
Operating Current
I
DD4W
TBD
2795
2795
rnA
I
DD3N
Auto Refresh Current
Self Refresh Current
I
DD5
I
DD6
TBD
TBD
3281
365
3281
365
mA
mA
I
DD3N
I
DD6
CKE
￡
0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
=t
(MIN);
t
=t
(MIN); Address and control
inputs change only during Active Read
or Write commands.
Operating Current
I
DD7A
TBD
5315
5315
mA
I
DD3N
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|---|---|
| W3EG7263S202JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S262AJD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S262D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S262JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S263AJD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
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