- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363885 > W3EG72255S-D3 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL PDF資料下載
參數(shù)資料
| 型號： | W3EG72255S-D3 |
| 英文描述： | 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| 中文描述： | 2GB的- 2x128Mx72 ECC的DDR SDRAM的注冊，瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 260K |
| 代理商： | W3EG72255S-D3 |
W3EG72255S-D3
-JD3
-AJD3
PRELIMINARY
6
White Electronic Designs
November 2004
Rev. 2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
+70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V.
Includes PLL and register power
Parameter
Operating Current
Symbol
I
DD0
Rank 1
Conditions
One device bank; Active - Precharge;
t
= t
(MIN); t
= t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
One device bank; Active-Read-
Precharge Burst = 2; t
= t
(MIN);
t
= t
(MIN); l
= 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down mode;
t
CK
= t
CK
(MIN); CKE = (low)
CS# = High; All device banks idle;
t
= t
(MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. V
IN
= V
REF
for DQ, DQS
and DM.
One device bank active; Power-Down
mode; t
CK
(MIN); CKE = (low)
CS# = High; CKE = High; One device
bank; Active-Precharge;t
= t
(MAX);
t
= t
(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once
per clock cycle.
Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; t
CK
= t
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
t
= t
(MIN); DQ,DM and DQS inputs
changing once per clock cycle.
t
RC
= t
RC
(MIN)
DDR333@CL=2.5
Max
4725
DDR266:@CL=2, 2.5
Max
4725
DDR200@CL=2
Max
4725
Units
mA
Rank 2
Standby
State
I
DD3N
Operating Current
I
DD1
5265
5265
5265
mA
I
DD3N
Precharge Power-
Down Standby Current
Idle Standby Current
I
DD2P
180
180
180
rnA
I
DD2P
I
DD2F
1930
1930
1930
mA
I
DD2F
Active Power-Down Standby
Current
Active Standby Current
I
DD3P
1260
1260
1260
mA
I
DD3P
I
DD3N
2110
2110
2110
mA
I
DD3N
Operating Current
I
DD4R
5355
5355
5355
mA
I
DD3N
Operating Current
I
DD4W
5535
5175
5175
rnA
I
DD3N
Auto Refresh Current
Self Refresh Current
I
DD5
I
DD6
7640
455
7640
455
7640
455
mA
mA
I
DD3N
I
DD6
CKE
≤
0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
=t
(MIN);
t
=t
(MIN); Address and control inputs
change only during Active Read or Write
commands.
Operating Current
I
DD7A
9675
9585
9585
mA
I
DD3N
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG72255S-JD3 | 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG7263S202AJD3 | 512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S202JD3 | 512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7263S202D3 | 512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG7264S202JD3 | 512MB - 64Mx72 DDR SDRAM UNBUFFERED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG72255S-JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG72256MS100AJD3MF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72256MS100AJD3MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72256MS100AJD3SF | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72256MS100AJD3SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。