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參數資料
| 型號： | W3EG7218S202BD4 |
| 英文描述： | 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| 中文描述： | 128MB的- 16Mx72 DDR SDRAM的緩沖瓦特/鎖相環 |
| 文件頁數： | 5/13頁 |
| 文件大小： | 177K |
| 代理商： | W3EG7218S202BD4 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
November 2004
Rev. 1
PRELIMINARY
W3EG7218S-AD4
-BD4
I
DD
SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, 0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V)
Parameter
Operating Current
Symbol Conditions
I
DD0
One device bank; Active - Precharge; (MIN); DQ,DM and DQS
inputs changing once per clock cycle; Address and control
inputs changing once every two cycles. t
RC
=t
RC
(MIN); t
CK
=t
CK
I
DD1
One device bank; Active-Read-Precharge; Burst = 2;
t
RC
=t
RC
(MIN);t
CK
=t
CK
(MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
I
DD2P
All device banks idle; Power-down mode; t
CK
=t
CK
(MIN);
CKE=(low)
I
DD2F
CS# = High; All device banks idle; t
CK
=t
CK
(MIN); CKE = high;
Address and other control inputs changing once per clock cycle.
V
IN
= V
REF
for DQ, DQS and DM.
I
DD3P
One device bank active; Power-down mode; t
CK
(MIN);
CKE=(low)
I
DD3N
CS# = High; CKE = High; One device bank; Active-Precharge;
t
RC
=t
RAS
(MAX); t
CK
=t
CK
(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
I
DD4R
Burst = 2; Reads; Continous burst; One device bank
active;Address andcontrol inputs changing once per clock
cycle; t
CK
=t
CK
(MIN); I
OUT
= 0mA.
I
DD4W
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t
CK
=t
CK
(MIN); DQ,DM and DQS inputs changing twice per clock
cycle.
I
DD5
t
RC
=t
RC
(MIN)
I
DD6
CKE ≤ 0.2V
I
DD7A
Four bank interleaving Reads (BL=4) with auto precharge with
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); Address and control inputs change
only during Active Read or Write commands
DDR266
@CL=2
DDR266
@CL=2.5
DDR200
@CL=2
Units
mA
Max
1125
Max
990
Max
990
Operating Current
1215
1080
1080
mA
Precharge Power-
Down Standby Current
Idle Standby Current
27
27
27
mA
405
405
405
mA
Active Power-Down
Standby Current
Active Standby Current
225
225
225
mA
450
450
450
mA
Operating Current
1260
1170
1170
mA
Operating Current
1260
1125
1125
mA
Auto Refresh Current
Self Refresh Current
Operating Current
2385
27
3195
1980
27
2970
1980
27
2970
mA
mA
mA
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相關代理商/技術參數 |
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|---|---|
| W3EG7218S262AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
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| W3EG7218S265AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7218S265BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7218S-AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
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