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參數資料
| 型號： | W3EG7217S202D3 |
| 英文描述： | 128MB - 16Mx72 DDR SDRAM REGISTERED, ECC w/PLL |
| 中文描述： | 128MB的- 16Mx72 DDR SDRAM的注冊，ECC的瓦特/鎖相環 |
| 文件頁數： | 6/12頁 |
| 文件大小： | 289K |
| 代理商： | W3EG7217S202D3 |
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7217S-D3
December 2004
Rev. 1
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes DDR SDRAM Component Only
Parameter
Operating Current
Symbol
I
DD0
Conditions
One device bank; Active = Precharge; t
RC
= t
RC
(MIN); t
CK
=
t
CK
(MIN); DQ,DM and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two
cycles.
One device bank; Active-Read-Precharge; Burst = 2; t
RC
=
t
RC
(MIN);t
CK
= t
CK
(MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
All device banks idle; Power- down mode; t
CK
= t
CK
(MIN);
CKE = (low)
CS# = High; All device banks idle; t
CK
= t
CK
(MIN); CKE =
high; Address and other control inputs changing once per
clock cycle. V
IN
= V
REF
for DQ, DQS and DM.
One device bank active; Power-down mode; t
CK
(MIN); CKE
= (low)
CS# = High; CKE = High; One device bank; Active-
Precharge; t
RC
= t
RAS
(MAX); t
CK
= t
CK
(MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t
CK
= t
CK
(MIN); I
OUT
= 0mA.
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t
CK
= t
CK
(MIN); DQ,DM and DQS inputs changing twice per
clock cycle.
t
RC
= t
RC
(MIN)
CKE
≤
0.2V
Four bank interleaving Reads (BL = 4) with auto precharge
with t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN); Address and control
inputs change only during Active Read or Write commands.
DDR266@CL = 2
Max
900
DDR266@CL = 2.5
Max
945
DDR200@CL = 2
Max
945
Units
mA
Operating Current
I
DD1
1080
1080
1080
mA
Precharge Power-
Down Standby Current
dle Standby Current
I
DD2P
27
27
27
mA
I
DD2F
405
360
360
mA
Active Power-Down
Standby Current
Active Standby Current
I
DD3P
225
180
180
mA
I
DD3N
450
405
405
mA
Operating Current
I
DD4R
1170
1125
1125
mA
Operating Current
I
DD4W
1125
1080
1080
mA
Auto Refresh Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
1980
27
2970
1980
18
2925
1980
18
2925
mA
mA
mA
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W3EG7217S262D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM REGISTERED, ECC w/PLL |
| W3EG7217S265D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM REGISTERED, ECC w/PLL |
| W3EG7217S-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM REGISTERED, ECC w/PLL |
| W3EG7218S202AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7218S202BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
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