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參數(shù)資料
| 型號(hào)： | W3EG72128S-D3 |
| 英文描述： | 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED |
| 中文描述： | 1GB的- 2x64Mx72 DDR內(nèi)存緩沖 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 245K |
| 代理商： | W3EG72128S-D3 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
W3EG72128S-D3
-JD3
May 2005
Rev. 3
ADVANCED
White Electronic Designs
I
DD
SPECIFICATIONS AND TEST CONDITIONS
V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V; DDR400: V
CC
= V
CCQ
= 2.6V ± 0.1V
Includes DDR SDRAM component only
Parameter
Operating Current
Symbol Conditions
I
DD0
One device bank; Active - Precharge;
t
=t
(MIN); t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
I
DD1
One device bank; Active-Read-
Precharge Burst = 2; t
=t
(MIN);
t
=t
(MIN); l
= 0mA; Address
and control inputs changing once per
clock cycle.
I
DD2P
All device banks idle; Power-down
mode; t
CK
=t
CK
(MIN); CKE=(low)
I
DD2F
CS# = High; All device banks idle;
t
=t
(MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. V
IN
= V
REF
for
DQ, DQS and DM.
I
DD3P
One device bank active; Power-
Down mode; t
CK
(MIN); CKE=(low)
I
DD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; t
=t
(MAX); t
=t
(MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
I
DD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
I
DD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
I
DD5
t
RC
= t
RC
(MIN)
I
DD6
CKE
≤
0.2V
I
DD7A
Four bank interleaving Reads (BL=4)
with auto precharge with t
=t
(MIN); t
=t
(MIN); Address and
control inputs change only during
Active Read or Write commands.
DDR400@
CL=3
Max
DDR333@
CL=2.5
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
DDR200@
CL=2
Max
Units
mA
2475
2070
2070
2070
2070
Operating Current
2745
2340
2340
2340
2340
mA
Precharge Power-
Down Standby Current
Idle Standby Current
90
90
90
90
90
rnA
990
810
810
810
810
mA
Active Power-Down
Standby Current
Active Standby Current
810
630
630
630
630
mA
1080
900
900
900
900
mA
Operating Current
2790
2385
2385
2385
2385
mA
Operating Current
2835
2475
2475
2475
2475
rnA
Auto Refresh Current
Self Refresh Current
Operating Current
4185
90
3510
90
3510
90
3510
90
3510
90
mA
mA
mA
5130
4545
4500
4500
4500
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| W3EG72128S-JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM UNBUFFERED |
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| W3EG72129S202JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL |
| W3EG72129S262JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM REGISTERED w/PLL |
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