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參數(shù)資料
型號(hào)： W3EG6433S262BD4
英文描述： 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL
中文描述： 256MB的- 32Mx64 DDR內(nèi)存緩沖，瓦特/鎖相環(huán)
文件頁(yè)數(shù)： 7/13頁(yè)
文件大小： 334K
代理商： W3EG6433S262BD4
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6433S-AD4
-BD4
May 2005
Rev. 1
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
AC CHARACTERISTICS
335
262
265/202
UNITS
NOTES
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
SYMBOL
t
AC
t
CH
t
CL
t
CK (2.5)
t
CK (2)
t
DH
t
DS
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
DQSQ
t
DQSS
t
DSS
t
DSH
t
HP
t
HZ
t
LZ
t
IHF
t
ISF
t
IHS
t
ISS
t
IPW
t
MRD
MIN
-0.70
0.45
0.45
6
7.5
0.45
0.45
1.75
-0.60
0.35
0.35
MAX
+0.70
0.55
0.55
13
13
MIN
-0.75
0.45
0.45
7.5
7.5
0.5
0.5
1.75
-0.75
0.35
0.35
MAX
+0.75
0.55
0.55
13
13
MIN
-0.75
0.45
0.45
7.5
7.5/10
0.5
0.5
1.75
-0.75
0.35
0.35
MAX
+0.75
0.55
0.55
13
13
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
26
26
CL = 2.5
CL = 2
40, 45
40, 45
23, 27
23, 27
27
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
+0.60
+0.75
+0.75
0.4
1.25
0.5
1.25
0.5
1.25
22, 23
0.75
0.20
0.20
t
CH,
t
CL
0.75
0.20
0.20
t
CH,
t
CL
0.75
0.20
0.20
t
CH,
t
CL
8
+0.70
+0.75
+0.75
16, 37
16, 37
12
12
12
12
-0.70
0.75
0.75
0.8
0.8
2.2
12
-0.75
0.90
0.90
1
1
2.2
15
-0.75
0.90
.900
1
1
2.2
15
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W3EG6433S265AD4 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W3EG6433S262D3 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED
W3EG6433S263D3 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED
W3EG6433S263JD3 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED
W3EG6433S265AD4 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL
W3EG6433S265BD4 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL
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