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參數(shù)資料
| 型號： | W3EG64255MS100JD3SG |
| 英文描述： | 2GB - 2x128Mx64 DDR SDRAM REGISTERED, w/PLL |
| 中文描述： | 2GB的- 2x128Mx64 DDR SDRAM的注冊，瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 216K |
| 代理商： | W3EG64255MS100JD3SG |
W3EG64255S-JD3
9
White Electronic Designs
April 2005
Rev. 3
ADVANCED
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
0°C ≤ T
A
≤ +70°C; V
CC
= +2.5V ±0.2V, V
CCQ
= +2.5V ±0.2V
AC Characteristics
335
262/263/265
202
Parameter
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to V
CC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Symbol
t
RCD
t
RP
t
RPRE
t
RPST
t
RRD
t
WPRE
t
WPRES
t
WPST
t
WR
t
WTR
NA
t
REFC
t
REFI
t
VTD
t
XSNR
t
XSRD
Min
18
18
0.9
0.4
12
0.25
0
0.4
15
1
Max
Min
20
20
0.9
0.4
15
0.25
0
0.4
15
1
Max
Min
20
20
0.9
0.4
15
0.25
0
0.4
15
1
Max
Units
ns
ns
t
CK
t
CK
ns
t
CK
ns
t
CK
ns
t
CK
ns
μs
μs
ns
ns
t
CK
Notes
1.1
0.6
1.1
0.6
1.1
0.6
19
10,11
9
0.6
0.6
0.6
t
QH
-t
DQSQ
t
QH
-t
DQSQ
t
QH
-t
DQSQ
13
12
12
70.3
7.8
70.3
7.8
70.3
7.8
0
0
0
75
200
75
200
80
200
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| W3EG64255MS133JD3GG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
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| W3EG64255MS133JD3SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG64255MS166JD3GG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG64255MS166JD3MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
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