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參數(shù)資料
| 型號： | W3EG128M72ETSU403D3 |
| 英文描述： | 1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| 中文描述： | 1GB的- 128Mx72 DDR SDRAM的無緩沖ECC瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 277K |
| 代理商： | W3EG128M72ETSU403D3 |
W3EG128M72ETSU-D3
-JD3
-AJD3
ADVANCED
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2005
Rev. 0
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
70°C, V
CC
= V
CCQ
= 2.5V ± 0.2V (100, 133, 166MHz), V
CC
= V
CCQ
= +2.6V ± 0.1V (200MHz)
Parameter
Operating Current
Symbol
I
DD0
Conditions
One device bank; Active - Precharge;
(MIN); DQ,DM and DQS inputs
changing once per clock cycle;
Address and control inputs changing
once every two cycles. T
RC
=T
RC
(MIN);
T
CK
=T
CK
One device bank; Active-
Read-Precharge; Burst = 2;
T
=T
(MIN);T
=T
(MIN); Iout
= 0mA; Address and control inputs
changing once per clock cycle.
All device banks idle; Power-down
mode; T
CK
=T
CK
(MIN); CKE=(low)
DDR400@
CL=3
DDR333@
CL=2.5
DDR266@
CL=2, 2.5
DDR200@
CL=2
Units
mA
Max
TBD
Max
TBD
Max
TBD
Max
TBD
Operating Current
I
DD1
TBD
TBD
TBD
TBD
mA
Precharge Power-
Down Standby
Current
Idle Standby Current
I
DD2P
TBD
TBD
TBD
TBD
mA
I
DD2F
CS# = High; All device banks idle;
T
=T
(MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. V
IN
= V
REF
for DQ,
DQS and DM.
One device bank active; Power-down
mode; T
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One
device bank; Active-Precharge;
T
=T
(MAX); T
=T
(MIN); DQ,
DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per clock
cycle.
Burst = 2; Reads; Continous burst;
One device bank active;Address
andcontrol inputs changing once
per clock cycle; T
CK
=T
CK
(MIN); I
OUT
= 0mA.
Burst = 2; Writes; Continous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; T
=T
(MIN); DQ,DM and
DQS inputs changing twice per clock
cycle.
T
RC
=T
RC
(MIN)
CKE ≤ 0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with T
=T
(MIN); T
=T
(MIN); Address and
control inputs change only during
Active Read or Write commands
TBD
TBD
TBD
TBD
mA
Active Power-Down
Standby Current
Active Standby
Current
I
DD3P
TBD
TBD
TBD
TBD
mA
I
DD3N
TBD
TBD
TBD
TBD
mA
Operating Current
I
DD4R
TBD
TBD
TBD
TBD
mA
Operating Current
I
DD4W
TBD
TBD
TBD
TBD
mA
Auto Refresh Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| W3EG128M72ETSU403JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU-AJD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU-JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG2128M64ETSR263JD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx64 DDR SDRAM REGISTERED w/PLL |
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