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參數資料
| 型號： | W39V040AQ |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 512K 】 8 CMOS FLASH MEMORY WITH LPC INTERFACE |
| 中文描述： | 512K X 8 FLASH 3.3V PROM, 11 ns, PDSO32 |
| 封裝： | 8 X 14 MM, STSOP-32 |
| 文件頁數： | 5/34頁 |
| 文件大小： | 384K |
| 代理商： | W39V040AQ |
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W39V040A
Publication Release Date: December 19, 2002
- 5 -
Revision A2
Hardware Data Protection
The integrity of the data stored in the W39V040A is also hardware protected in the following ways:
(1)
Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2)
V
DD
Power Up/Down Detection: The programming and read operation is inhibited when V
DD
is less
than 1.5V typical.
(3)
Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
(4)
V
DD
power-on delay: When V
DD
has reached its sense level, the devices will automatically time-out 5
mS before any write (erase/program) operation.
Data Polling (DQ
7
)- Write Status Detection
The W39V040A includes a data polling feature to indicate the end of a program or erase cycle. When
the W39V040A is in the internal program or erase cycle, any attempts to read DQ
7
of the last byte
loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ
7
will show the true data. Note that DQ
7
will show logical "0" during the erase cycle, and become logical
"1" or true data when the erase cycle has been completed.
Toggle Bit (DQ
6
)- Write Status Detection
In addition to data polling, the W39V040A provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
6
will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.
Multi-Chip Operation
Multiple devices can be wired on the single LPC bus. There are four ID pins can be used to support up to
16 devices. But in order not to violate the BIOS ROM memory space defined by Intel, Winbond
W39V040A will only used 3 ID pins to allow up to 8 devices, 4Mbytes for BIOS code and 4Mbytes for
registers memory space.
Register
There are two kinds of registers on this device, the General Purpose Input Registers and Product
Identification Registers. Users can access these registers through respective address in the 4Gbytes
memory map. There are detail descriptions in the sections below.
General Purpose Inputs Register
This register reads the states of GPI[4:0] pins on the W39V040A. This is a pass-through register, which
can be read via memory address FFBxE100(hex). The "x" in the addresses represents the ID [3:0] pin
straps. Since it is pass-through register, there is no default value.
相關PDF資料 |
PDF描述 |
|---|---|
| W39V040BQ | W39V040B |
| W39V040BQZ | W39V040B |
| W39V040B | W39V040B |
| W39V040BP | W39V040B |
| W39V040BPZ | W39V040B |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W39V040B | 制造商:WINBOND 制造商全稱:Winbond 功能描述:W39V040B |
| W39V040B_07 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE |
| W39V040BP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:W39V040B |
| W39V040BPZ | 制造商:WINBOND 制造商全稱:Winbond 功能描述:W39V040B |
| W39V040BQ | 制造商:WINBOND 制造商全稱:Winbond 功能描述:W39V040B |
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