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參數資料
| 型號： | W39L040AP70B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 512K 】 8 CMOS FLASH MEMORY |
| 中文描述： | 512K X 8 FLASH 3.3V PROM, 70 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數： | 6/26頁 |
| 文件大小： | 231K |
| 代理商： | W39L040AP70B |
W39L040A
- 6 -
Byte 0 (A0 = V
IL
) represents the manufacturer
′
s code (Winbond = DAH) and byte 1 (A0 = V
IH
) the
device identifier code (W39L040A = D6hex). All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Auto-select, A1 must be low state.
6.2 Data Protection
The W39L040A
is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from V
DD
power-up and power-down transitions or system noise.
6.2.1
To avoid initiation of a write cycle during V
DD
power-up and power-down, the W39L040A locks out
when V
DD
< 2.0V (see DC Characteristics section for voltages). The write and read operations are
inhibited when V
DD
is less than 2.0V typical. The W39L040A ignores all write and read operations until
V
DD
> 2,0V. The user must ensure that the control pins are in the correct logic state when V
DD
> 2.0V
to prevent unintentional writes.
Low
V
DD
Inhibit
6.2.2
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.
Write Pulse "Glitch" Protection
6.2.3
Writing is inhibited by holding any one of #OE = V
IL
, #CE = V
IH
, or #WE = V
IH
. To initiate a write cycle
#CE and #WE must be a logical zero while #OE is a logical one.
Logical Inhibit
6.2.4
Power-up of the device with #WE = #CE = V
IL
and #OE = V
IH
will not accept commands on the rising
edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state
machine is automatically reset to the read mode on power-up.
Power-up Write and Read Inhibit
6.3 Command Definitions
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. "Command Definitions" defines the valid register command sequences.
6.3.1
The device will automatically power-up in the read state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory content occurs during the power transition.
The device will automatically returns to read state after completing an Embedded Program or
Embedded Erase algorithm.
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Read Command
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